In this era of technology revolution, there is a continuous progression in domains like AI applications, high end servers, and graphics. These applications require fast processing and high densities for storing the data, where High Bandwidth Memory (HBM) provides the most viable memory technology solution. Our previous memory blog HBM2 memory for graphics, networking and HPC explored this protocol with data transfer rate of 2GT/s with stacked architecture of 8-Hi stacks (8 die).The HBM2-extension (HBM2E) architecture provided further improvement on top of HBM2 with 3.2 GT/s transfer rate and 12-Hi stack architecture with individual die density upto 8Gb and overall density of 24GB.
The HBM3 architecture provides a die density of 16Gb with 16-Hi stack thus providing a total density of 64GB. The maximum data transfer rate with HBM3 can go up-to 6.4GT/s.
HBM3: The future of DRAM technology
HBM3 is a 3D DRAM technology which can stack upto 16 DRAM dies, interconnected by Through-Silicon Vias (TSVs), and microbumps.
Lets take a quick look at key differentiating features in HBM3.
Like HBM2 architecture, HBM3 provides two independent row and column command interfaces, allowing activates/precharges to be issued in parallel with reads/writes. This simplifies controller operations and increases bandwidth. HBM3 supports DQ width of 64 bits with 8n prefetch architecture thus allowing 512 bits of memory read and write access. HBM3 has a pseudo channel mode architecture, which divides a channel into two individual sub-channels of 32 bit I/O each.
HBM3 has a dual clocking architecture, DDR clock for command and DDR WDQS clock for data. The WDQS clock, which is 2X the command clock, is driven by controller for both read and write operations.
HBM3 also has a provision for on chip ECC calculation for error detection and severity pins to indicate the severity of errors. HBM3 devices will support read/write meta data bits, error scrubbing mechanism, error transparency protocol and fault isolation limits , which will help to achieve high system Reliability, Availability and Serviceability (RAS). The severity transmission to the host helps in providing the feedback to the host about the error type.
HBM3 has also introduced new trainings, namely, WDQS2CK training (Write Leveling), WDQS Oscillator, and Duty Cycle Correction. These trainings are taken from new DRAM families like DDR5 and LPDDR5.
To conclude, HBM3 is a breakthrough memory solution for performance, power and form factor constrained systems, delivering high-bandwidth, and high density. With a 16-channel stacked architecture, HBM3 provides the one of the best form factors.
Stay tuned for upcoming blogs on the emerging next-generation HBM standard and a deeper dive into HBM3 features. Synopsys provides VIP for HBM3/HBM2/HBM , including the IEEE test mode, along with run time configurable timing parameters, extensive timing and data integrity checks, and integration with Verdi Protocol Analyzer and Verdi Performance Analyzer. For more information on Synopsys memory VIP and test suite, please visit http://synopsys.com/vip