Data is the new fuel powering critical use-cases for cloud /edge computing, and advances in AI. All aspects of data handling – gathering, storing, moving, processing, and dispersing – pose unique design implementation and verification challenges. The need for heterogenous computing has given exponential rise to application specific accelerators, pushing the industry to come up with a solution for efficient data handling and resource utilization. CXL is a processor interconnect protocol designed to support high bandwidth, low-latency interface from CPU to workload accelerators, maintaining memory coherency across heterogeneous devices, while addressing security needs of the user.
Verification and Validation Challenges around CXL Systems
CXL standard presents a blend of peripheral interconnect, memory, coherency, and security domains. Below are the important points to consider when approaching verification of CXL systems.
Fusion of domain expertise is key for realizing CXL systems & Synopsys leverages several decades of expertise to provide a comprehensive offering for enabling development of CXL based designs for its users. CXL Protocol Continuum from Synopsys – is a comprehensive and complete solution spanning architecture exploration, system design and implementation, functional verification and acceleration, software development, system validation, compliance testing, and interoperability of complete system.
Synopsys has a strong participation in the CXL Consortium, and has been a leading partner in driving the adoption, contribution to CXL standards to enable a wide variety of system-based applications and giving early advantage for Interop testing of latest of the CXL-CV compliance tests on our continuum solutions. Synopsys is a leading provider of DesignWare CXL IPs and PHYs, including CXL 2.0 Integrity and Data Encryption (IDE) Security IP Module compliant with the defined CXL 2.0 IDE specification.
Our offerings in Protocol Verification solutions are natively integrated with other Synopsys verification technologies including across-the-board Debug with Verdi, regression management and automation with VC Execution Manager (“ExecMan”).
Exciting and challenging times ahead for IP and chip design and verification engineers who are targeting to support a new and rapidly evolving specification. More information on Synopsys CXL VIP is available on Synopsys CXL VIP page and be sure to contact Synopsys experts for the latest development on this quickly evolving protocol. Stay tuned to hear more on CXL 3.0.
Fun Fact – In the last 3 years target addressable market for data accelerators has grown 7 Folds from $1.6B to around $12B today