The Compute Express Link (CXL) 1.1 and CXL 2.0 specification differ in the way memory mapped registers are placed and accessed. The CXL 1.1 specification places memory mapped registers in RCRB (Root Complex Register Block) while the CXL 2.0 specification links memory mapped registers in BAR (Base address ranges) of the device. In this blog we will focus on how to access CXL 2.0 specification memory mapped registers.
Register locator DVSEC (Designated Vendor Specific Extended Capability), available in the configuration space, acts as a link to access memory mapped registers. DVSEC contains register blocks which in-turn contain information of BAR allocated for memory mapped registers like component registers, memory device registers and BAR virtualization registers.
The examples below show the overall structure of register locator DVSEC, where each register block has offset low and offset high which specifies the register associated with that block.
For example, Register BIR having a value of 1h indicates an offset within BAR1 of the device.
This register locator DVSEC is mandatory for CXL 2.0 root port, CXL 2.0 device, CXL downstream and upstream switch port. This DVSEC is optional for CXL 1.1 devices and CXL 1.1 upstream and downstream ports.
In upcoming blogs, we will discuss CXL 2.0 cache-mem capabilities in component registers and how it can be leveraged per your needs. For more information on Synopsys VIP CXL visit: https://www.synopsys.com/verification/verification-ip/subsystems/compute-express-link.html