Coherent Hub Interface, popularly known as CHI, is an Interface specification that is part of 5th generation of AMBA® protocols (AMBA® 5) from Arm, released in 2013. AMBA® 5 CHI defines the interfaces for connection of fully coherent processors and dynamic memory controllers, to high performance non-blocking interconnects.
AMBA®CHI-E built on top of existing AMBA® CHI-D (Issue D) specification (refer to our blog on AMBA®CHI-D), introduces the support for– a set of new transactions, exclusive access features, transaction optimizations, series of performance throughput improvement features and key Arm architecture features.
Some of the new features include:
It’s nice that your system works well when unstressed, but what happens when you’re running at speed and there’s a lot of traffic churning through those coherent networks? Here Synopsys provides a capability called VC VIP Auto Performance which will generate traffic following the AMBA® Adaptive Traffic Profile (AMBA® ATP). (You need to create a test profile as input to this tool.) Subsequently you can analyze for latency and bandwidth problems in Verdi Performance Analyzer.
All the latest features are fully supported and available in Synopsys verification IP for AMBA® 5 CHI. Synopsys solution for AMBA® 5 CHI, provides performance metrics for latency and throughput analysis, comprehensive system level checks for protocol, data integrity and cache coherency. Built-in sequence collection, functional coverage model, verification plans, and a set of usage examples are also included to speed up verification coverage closure. Synopsys VIP is natively integrated with the Synopsys Verdi® Protocol Analyzer debug solution as well as Synopsys Verdi® Performance Analyzer.
More information on Synopsys AMBA® VIP and Test Suites is available at http://synopsys.com/vip
Read our blogs on AMBA®CHI Issue D(CHI-D), know more about verification automation solutions of Arm based protocols.