In the CXL ecosystem the host software uses enumeration as the first step to discover CXL devices connected in the system.
During this process it identifies whether the connected devices in the CXL ecosystem are one of following device types – PCIe, CXL 1.1 or CXL 2.0. It determines this based on PCIe configuration space and CXL specification defined capability and configuration registers.
This blog will focus on CXL 2.0 Device Discovery.
CXL 2.0 specification defined multiple new PCIe designated vendor-specific extended capabilities (DVSEC) in the PCIe configuration space mapped registers. The following are some of the mandatory DVSEC for CXL 2.0 Device.
CXL 1.1 devices appear as an RCiEP (Root Complex Integrated Endpoint) device in enumeration hierarchy. To make CXL 2.0 devices visible to the OS, they must get discovered as standard PCIe endpoint with a Type0 header. The presence of CXL DVSEC (Vendor ID 1e98) with DVSEC ID ‘0’ helps to distinguish between PCIe endpoint or CXL 2.0 device.
Examples of the complex CXL 2.0 topology can be observed in the image below, showing the CXL Root Port can be connected to any of these named devices:
The CXL 2.0 control and status registers (CSR) also utilizes PCIe configuration space and BARs (Base Address Register) for memory mapped registers resulting in the complexity for capability discovery and subsequently for configuration control and status monitoring.
Overall CXL 1.1/2.0 device configuration and status register space is very diverse.
Stay tuned for our upcoming blogs on the fascinating path of CXL 2.0 discovery & register space.