The Joint Electron Device Engineering Council (JEDEC) has been developing and maintaining DRAM standards for years, defining emerging Memory standards like the DRAM standard. The most recent announcement declares the fifth generation of the DRAM, DDR5, is finally ready for release. The work to define DDR5 began in 2017 with the objective of delivering a standard that could move beyond the DDR4 speed limitations of 16 Gb and 3200 MT/s. The intention was to address new applications around data centers high-end servers for handling AI/ML workloads.
Compute Express Link (CXL) is the latest specification in interconnect technology for high bandwidth devices. It provides high-speed, efficient connectivity from CPUs to other components of the high-performance computing platform.
HDMI (High-Definition Multimedia Interface) has been a part of our entertainment systems for nearly two decades now. Though the look of the cable has remained the same over the years, the input has undergone many improvements since its release in 2002.
Increasing complexities of processor architectures with limited overall performance scale-up have created a demand for a domain specific architecture to ensure extensive performance scaling. – this is when RISC-V began to gain momentum. RISC-V is gathering widespread attention throughout sectors like datacenter accelerators, mobile & wireless, IoT, etc. for its extensibility. Many industry leaders are beginning to adopt RISC-V for its open source availability that reduces time-to-market and cost effectiveness while at the same time scaling up the overall performance and leaving room for innovation and automation.
HDMI ARC, What is it and Why You Should Care?
Performance continues to be key factor for the design of any complex system-on-chip (SoC). Moreover, complexity is increasing every day, which poses a challenge for engineers to track performance of the design, yet they are tasked to continuously increase chip performance. When it comes to run time performance engineers not only develop the functionality but also can check performance of the design which is getting impacted from the new module. In traditional approach functionality development and performance analysis are sequential task and executed one after the other.