JEDEC recently announced the ratification of JESD79-5 DDR5 SDRAM to support the standardization of next-generation memory devices, catering to demand from rapid expansion in high performance computing and data center applications. This new standard promises to deliver 2X memory bandwidth, 4X larger density dies, and much improved power efficiency (1.1V Vdd). The DDR5 DIMM will operate in dual-channel mode all on its own, with two 40-bit fully independent sub-channels on the same module.
Additional DDR5 capabilities include:
In conjunction with the release of the new JESD79-5 DDR5 SDRAM standard, Synopsys released the industry’s first VIP for DDR5 DRAM/DIMM that provides native SystemVerilog Universal Verification Methodology (UVM) architecture and comprehensive feature sets. These features enable not only ease of integration and usage within existing verification environments but also are optimized for simulation performance speed up, allowing users to run greater number of tests and accelerate regression turnaround time.
The Synopsys Memory VIP portfolio supports verification of Controller, PHY as well as Memory devices. VC VIP for DDR5 is natively integrated with Synopsys’ Verdi® Protocol and Performance Analyzer and includes an exhaustive set protocol and timing checks, built-in coverage and verification plans for faster verification closure.
The comprehensive DRAM/DIMM and Flash memory VIP portfolio from Synopsys, including DDR5/4/3/2, 3DS, MRAM, DDR5 NVDIMM-P, LPDDR5/4/3/2, GDDR6, DFI 5.0, HBM2/2E/3, and latest SPI (Quad, Octal and xSPI)/NAND/ONFI, provides customer with support of latest memory technologies for emerging applications.
By working closely with standard organizations, such as JEDEC, and memory vendors Synopsys is able to deliver and deploy first-in-industry customer-proven solutions, allowing designers to adopt the latest memory technologies rapidly. Synopsys VC VIP for DDR5 DRAM/DIMM is available today. For more information, visit VC Verification IP for DDR5.