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Automating Testbench Creation to Accelerate Network-on-Chip Verification

Network-on-Chip (NoC) is a critical building block for many advanced and complex system-on-chips (SoCs). Having a complete verification solution to verify the functionality along with the performance (latency/bandwidth) is a must to ensure there are no functional bugs and no performance bottlenecks.

To verify the NoC extensively, it requires a robust verification environment. Creating such an environment and successfully passing the first test takes several weeks of effort. Therefore, there is a pressing need for automation to generate an error free verification environment, which can reduce the creation of verification environment from weeks to days.

NoCs are becoming increasingly complex with the introduction of cache coherency and cache and snoop filters within the NoC. To complete the functional verification and ensure that coherency is maintained across the NoC, a system-level monitor is a must have in order to check that coherency is maintained across the system. Further, a mechanism to generate performance stimulus and identify performance bottlenecks in necessary to flush out any latent issues.

To dive deeper into the verification closure process and automated testbench solution to address the challenge of NoC verification, you can now register for our Webinar.

Register : https://readytalk.webcasts.com/starthere.jsp?ei=1318019&tp_key=e5a11b55d0&sti=pmm

Web event: June 10th, 10:00 AM PST