The Joint Electron Device Engineering Council (JEDEC) has been developing and maintaining DRAM standards for years, defining emerging Memory standards like the DRAM standard. The most recent announcement declares the fifth generation of the DRAM, DDR5, is finally ready for release. The work to define DDR5 began in 2017 with the objective of delivering a standard that could move beyond the DDR4 speed limitations of 16 Gb and 3200 MT/s. The intention was to address new applications around data centers high-end servers for handling AI/ML workloads.
Today, DDR5 comes with a significant increase in Data Rates (3200MT/s to 6400MT/s), Memory interface bandwidth (51.2GB/s) and Density (8Gb to 64Gb). DDR5 technology is enabled with lots of new features related to Performance (More number of Banks, Bank Groups, BL16, Enhanced refresh modes, DFE), Reliability (On die ECC, Data CRC for Reads), Low Power (Write Pattern, Lower voltage levels for VDD/VDDQ/VPP), and Enhanced PHY trainings (CS training, Read training patterns, Internal write levelling, Improved CA training) in order to handle high frequency and accuracy requirements. These features allow up to 30% higher bandwidth even when operating at DDR4 speed.
DDR5 comes with higher speeds and a smaller footprint. It also promises higher power efficiency due to the reduction in voltage requirement, from 1.2V to 1.1V. The reduction in voltage requirement brings in additional complexity for DIMM vendors around noise immunity. It will require additional features, such as decision feedback equalization, to improve the data eye. Higher speeds and lower voltage are also going to add complexity to signal integrity, requiring an additional training mechanism to ensure proper operation. This would in turn increase the verification complexity, necessitating visualization and modeling of real-world scenarios and their coverage.
Most major Memory vendors have already published plans for releasing DDR5 Memory devices. They have already begun sampling their next-generation DDR5 devices built on the 10nm-class (1z) process. With DDR5 at 4800 MT/s, Memory vendors are seeing an ~85% performance improvement over DDR4 at 3200 MT/s. Performance is expected to increase multi fold as higher speed bins are in production.
It is anticipated that DDR5 will eventually capture a major share of the DDR4 market. The immediate utilization is expected to be around high-end servers and data centers, but it will likely also be used in desktops and laptops eventually. The integrated Memory controllers from leading processor companies are expected to adopt DDR5 soon.
Synopsys Verification IP (VIP) supports the JEDEC® Memory Device DDR5 SDRAM standard and has a complete verification solution available. The Synopsys VIP for DDR5 is compatible with the industry-standard Universal Verification Methodology (UVM) and runs on all leading simulators. DDR5 VIP, supporting both DRAM and DIMM configurations, is deployed at market leaders targeting high-end servers, cloud and next-gen computing. For more information, please visit http://synopsys.com/vip