Increasing complexities of processor architectures with limited overall performance scale-up have created a demand for a domain specific architecture to ensure extensive performance scaling. – this is when RISC-V began to gain momentum. RISC-V is gathering widespread attention throughout sectors like datacenter accelerators, mobile & wireless, IoT, etc. for its extensibility. Many industry leaders are beginning to adopt RISC-V for its open source availability that reduces time-to-market and cost effectiveness while at the same time scaling up the overall performance and leaving room for innovation and automation.
TileLink is an open standard chip-scale interconnect designed to be used with RISC-V processors. It also supports other ISAs.
TileLink is an easy to implement cache-coherent bus protocol that can be utilized in a System-on-Chip (SoC) to connect accelerators, general purpose multiprocessors, co-processors, DMA engines and simple or complex designs.
Wonder what TileLink has in store?
Key features of TileLink:
TileLink follows a Directed Acyclic Graph (DAG) topology where agents are vertices and links are edges directed from Primary to Secondary interfaces. Each link consists of a set of 2 mandatory channels (channel A & D) and 3 optional channels (channel B, C & E required for TL-C). To ensure deadlock freedom, TileLink specifies a prioritization among channels to be followed strictly:
A << B << C << D << E is the order of increasing priority levels for channels A, B, C, D and E.
Requests are always initiated by Primary on request channel and it then waits for a response from secondary on response channel.
Three conformance levels
TileLink may support operations such as Put, Get, Atomic, Hint, Acquire, Probe & Release based on the 3 conformance levels TL-UL, TL-UH & TL-C.
TileLink implements the Valid-Ready handshake, but leaves Valid and Ready assertion-deassertion, independent of each other in a manner that it allows Primary to discard any message which is yet to be accepted by Secondary. TileLink supports Out-of-Order, FIFO order, Delayed & Concurrent responses but does not support interleaving.
Since DAG assures TileLink of response for each request, timeouts are forbidden in TileLink. However, TileLink to legacy BUS bridges shall implement timeouts to fit within the aegis of first forward progress rule. If the response from legacy BUS do not arrive in time, the request must be discarded and a TileLink error response shall be inserted.
Stay Tuned for Synopsys’ comprehensive verification solution for TileLink with integrated Verdi Debug.