Performance continues to be key factor for the design of any complex system-on-chip (SoC). Moreover, complexity is increasing every day, which poses a challenge for engineers to track performance of the design, yet they are tasked to continuously increase chip performance. When it comes to run time performance engineers not only develop the functionality but also can check performance of the design which is getting impacted from the new module. In traditional approach functionality development and performance analysis are sequential task and executed one after the other.
Synopsys’ Verdi Performance Analyzer enables run time metrics to help achieve desired chip performance. Verdi Performance Analyzer lets functionality developers to do performance-based checks at early run time. This blog walks through taking memory protocol example, but the flow is protocol independent and applicable to all SoC designs.
A typical SOC design is comprised of many subsystems such as memory subsystem, interconnect bus, and processor, verification of each is done independently using UVM based VIP’s.In a UVM based environment, the controller is designed to send test stimulus to the verification IP, results of which can be studied through the VIP itself. VIP can provide performance data that can be utilized in analyzing the system performance and help with finding the software and hardware bottlenecks.
The API’s are written in system Verilog language which is easy to integrate in any test bench. Verdi Performance Analyzer solution allows to create instances based on the time slice (default is entire simulation time) and can be further used to create custom configuration and setting constraint values. User can add break point and evaluate the performance up to the time needed. The enabling and disabling of performance analysis is a key advantage to many designers to reach to exact performance loopholes within minimum duration. If a small range of transactions are faulty within the complete simulation, the performance metrics can be enabled only during that time hence utilizing lesser memory and time. Support of this feature is available for all the Synopsys protocols. Detailed steps for HBM2/2E VIP is captured in white paper at below link.
Be sure to read some of our other recent memory VIP blogs: