Posted by VIP Experts on November 4, 2019
Synopsys offers a broad set of verification solutions for next generation Arm® AMBA® protocols, including AMBA5 CHI Issue D(CHI-D), and verification automation solutions including VC AutoTestbench for Testbench Generation and VC Autoperformance for Performance Verification of ARM based protocols, which designers have widely adopted and achieved numerous tape-out successes. We continue the rapid expansion of Synopsys’ verification solutions for AMBA protocols and strengthen our leadership with our latest offering of VIP for AMBA ACE5 and AXI5, which are already in use by early adopters of the new specifications. Synopsys VIP for the AMBA5 CHI Issue D (CHI-D) specification enabled early customers and partners to extend the standard architecture for their next-generation coherent designs with new enhancements for increased performance. Let’s dive down to understand more about the new features and latency optimization techniques available in AMBA5 CHI Issue D.
Coherency is the crux to most of the today’s complex SoCs targeting wide range of applications, such as: mobile, networking, AI/machine learning, automotive, and data centers. CHI is built on the same coherency protocol that is used in AMBA 4 ACE. CHI operates on the concept of Nodes and Interfaces, rather than the Master/Slave paradigm used by previous AMBA protocols. A CHI master is termed as Request Node (RN), CHI slave is termed as Slave Node (SN). The CHI interconnect consists of one or more Home Nodes (HN).
Coherent Hub Interface, popularly known as CHI, is an Interface specification that is part of 5th generation of AMBA protocols (AMBA5) from ARM, released in 2013. AMBA5 CHI defines the interfaces for connection of fully coherent processors and dynamic memory controllers, to high performance, non-blocking interconnects i.e. Hubs. CHI ensures that the interconnect never becomes the bottleneck in a scalable system with large number of coherent CPUs.
CHI-D introduces the support for key ARM Architecture features, a series of performance improvement features, transaction latency improvement features, and Functional Safety (FuSa) features. All these features are aligned with the requirements for the next generation Mobile, Automotive, Infrastructure (Networking and Data Center) system on chips (SoCs).
CHI-D: Key Features
• MPAM (Memory System Resource Partitioning and Monitoring) Support: Enables ARMV8.4-A architecture compliant MPAM Identifiers to be attached to CHI Transactions, and the same are transported through AMBA5 CHI-D Interfaces to various system components. One of the use cases is in case of servers– where there are foreground and background jobs, and the requirement is that foreground job’s response time should not be compromised, and the background job’s throughput should be optimized. The performance of the foreground and background jobs can be monitored with the help of MPAM IDs, and the resource allocations can be changed dynamically to optimize foreground response time and background throughput.
• Deep Persistent Memory Support: Aligns with ARMV8.5-A Architecture compliant Deep Persistent Memory features through Persistent CMOs (Cache Maintenance Operations) with two-part responses and Deep Persistent CMOs.
Performance Improvement and Latency Optimization Features
• Increased Number of Outstanding Transactions: Allows an increase in number of outstanding transactions from 256 to 1024, that is required for high latency chip-to-chip interfacing.
• Completer Busy Indication: Completer of a transaction can indicate its current level of activity, so that the Requester can, for example, determine how aggressively it can generate speculative activity to improve performance. This helps to fine tune system performance.
• Early Completions for DVM (Distributed Virtual Memory) Transactions: Improves the latency for DVM Transactions generated from RN, by permitting Interconnect to generate Early Completions. This enables greater number of DVM Transactions to be pipelined from a single RN.
• Avoid broadcasting of Instruction Cache invalidations: Interface configuration to support coherent instruction caches, allowing disabling of instruction cache Invalidation DVM (Distributed Virtual Memory) Transactions.
• Latency Improvements to Ordered Write Observation Flow: Rules pertaining to Ordered Write Observation Flow are relaxed, so that the latency for such Ordered Stream of Write Transactions at RN is optimized. The Ordered Write Observation Flows are extended to Non snoopable Write Transactions as well.
Functional Safety (FuSa) Features
• Interface Parity Protection: Used in applications such as automotive, which have resilience or functional safety requirements; as well as data center applications which have resilience requirements. This feature is being introduced across all the AMBA interfaces, so that end-to-end protection of on-chip communications is enabled by AMBA Interface Parity Protection. This helps in detecting faults between two components connected through an AMBA interface.
Synopsys solution for AMBA5 CHI-D, provides performance metrics for latency and throughput analysis, configurable interconnect model, a reference verification platform and system level checks for protocol, data integrity and cache coherency. Built-in coverage and verification plans are also included to speed up verification coverage closure. In addition, VIP is natively integrated with the Synopsys Verdi® Protocol Analyzer debug solution as well as Synopsys Verdi® Performance Analyzer. To learn more about Synopsys VIP and test suites for AMBA protocols, please visit http://synopsys.com/vip