Verification Central


Come sprint with the champs at JEDEC DDR5, LPDDR5 & NVDIMM-P Workshops & Trainings

We are excited to attend the upcoming JEDEC workshops and tutorial in Santa Clara, October 7th – 10th. The workshops will provide an introduction and in-depth technical review of the DDR5, LPDDR5 and NVDIMM-P standards as well as present the latest reliability and optimization features.

Synopsys’ own Rajesh Mahajan and Brett Murdock will be presenting an LPDDR5 System Training on Monday, and on Thursday Tsun Ho Liu will be presenting a session covering NVDIMM-P initialization, interface training and registers for DDR4 and DDR5 NVDIMM-P modules. You can check out the detailed event agendas here.

Synopsys works closely with JEDEC, and together we have created an excellent set of Memory Verification IP (VIP) for DDR5/4/3, LPDDR5/4/3, NVDIMM-P/N, that complements Synopsys’ other VIP for Flash, MIPI, PCIe, AMBA, Ethernet, HDMI, SATA, etc…

The unique and flexible architecture of Synopsys Memory VIP makes it possible to be easily plugged in to any Verilog/SV/UVM/VMM based testbench setup. For more information visit our webpage. If you are interested in learning more about the Synopsys VIP solution or interested in a deep dive VIP overview session please contact us.

Don’t miss the chance, register today for the JEDEC workshops. We’ll see you there!