Posted by VIP Experts on October 2, 2019
HBM2E (High Bandwidth Memory) is a high-performance 3D-stacked DRAM used in high-performance computing and graphic accelerators. It uses less power but posts higher bandwidth than graphics cards relying on DDR4 or GDDR5 memory. Validating the performance and utilization of memory is a big challenge for users due to complex structure of SoC and the subsystem attached to it such as memory subsystem, interconnect bus, and processor.
Synopsys’ Verdi Performance Analyzer provides a solution. This blog will provide insight into how Verdi Performance Analyzer natively integrated with Synopsys VIP can be used to measure key performance metrics like number of commands, count of page empty scenarios that occur in a test. All of these metrics can be used for performance benchmarking.
Memory Transaction Flow
The basic memory access flow can be described as opening a bank using an Activate command, followed by Writing or Reading from various addresses in the bank, and finally closing the bank using a precharge command.
Figure 1 – HBM Memory Transaction
Verdi Performance Analyzer
The number of cmd metric is categorized as single value metric and displayed in the tool as shown below.
In ‘page empty scenario’, we have two types of questions that can be answered by the tool: 1- How many scenarios exist? 2- What is the latency for each of them?
To answer question 1, single value metrics are shown by the tool.
The answer to question 2 requires multi-valued metrics and is displayed as bar chart.
Metrics like latency between commands, bandwidth, bus idle time and various scenarios of page-empty, page-miss, page-hit latencies are also important to be captured and can be used in benchmarking. You can read a more detailed performance analysis for HBM here: https://www.synopsys.com/cgi-bin/verification/dsdla/pdfr1.cgi?file=hbm-vip-wp.pdf
Be sure to read some of our other recent memory VIP blogs:
A global team of protocol experts that share their insights and technical expertise in the areas of Automotive, DRAM and Flash Memories, Storage, Display, MIPI, AMBA, Ethernet, PCIe, USB and many other bus and interface protocols. This comprehensive team participates in standards committees and will provide the latest information and updates as it relates to your future design considerations.