Posted by VIP Experts on September 23, 2019
Looking for ways to reduce debug cycles to quickly root cause the issues in your Memory Controller/PHY and Subsystem Verification Project?
At some point, you have most likely faced one of the following challenges while debugging a memory model (Timing Issues, Log Messages, Bank Stats, Layered Debug, etc..)
Synopsys Memory Model (VIP), together with Verdi increases your overall debugging productivity. Below are examples of how the tightly coupled debug solution will help to address some of the pain points:
Below are additional examples with detailed descriptions for your reference:
The unique, flexible architecture of Synopsys Memory VIP makes it possible to be easily plugged in to any Verilog/SV/UVM/VMM based testbench setup. For more information visit, https://www.synopsys.com/verification/verification-ip/memory.html
Synopsys supports over 90+ Industry Leading Verification IP and source code Test Suites for protocols such as Arm® AMBA®, DRAM Memory (DDR5, LPDDR5), Flash Memory, Ethernet (400G), MIPI, PCIe (5.0), SAS, SATA, USB (4.0/3.x, Type-C). For a complete list of Verification IP and Test Suites, visit www.synopsys.com/vip.
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A global team of protocol experts that share their insights and technical expertise in the areas of Automotive, DRAM and Flash Memories, Storage, Display, MIPI, AMBA, Ethernet, PCIe, USB and many other bus and interface protocols. This comprehensive team participates in standards committees and will provide the latest information and updates as it relates to your future design considerations.