Posted by VIP Experts on September 16, 2019
Looking for a way to reduce effort defining and tracking functional verification goals in your Memory Controller/PHY and Subsystem Verification Project?
If you have not already deployed best practices of using Verification Plans, Functional and Timing Coverage Models in your Memory projects, learn why it is recommended…
Key Attributes of Functional and Timing Coverage Closure Flow
Synopsys Memory Models (VIP) have built in verification plans, functional and timing coverage models to accelerate coverage closure. The coverage models are provided to help run complete verification scenarios across multiple combinations of configuration settings, mode register settings, features, and timing parameters.
Synopsys Memory VIP supports the latest ratified and draft specifications from standards organizations such as JEDEC, ONFi, SD, and SPI (DDR5, LPDDR5, DFI 5.0, HBM3, GDDR6, and NVDIMM-P/N) and native integrations and optimizations with VCS and Verdi.
Coverage model implementation is based on System Verilog constructs (covergroups, coverpoints, bins, illegal bins) and it is “Protocol Specification Version aware” which means coverpoints/bins are ignored if not applicable to the configured protocol specification version.
Synopsys Memory VIP coverage models comprise of,
The unique, flexible coverage architecture of Synopsys Memory VIP makes it possible to be easily plugged in to any Verilog/SV/UVM/VMM based testbench setup. For more information visit, https://www.synopsys.com/verification/verification-ip/memory.html
Synopsys supports over 90+ Industry Leading Verification IP and source code Test Suites for protocols such as Arm® AMBA®, DRAM Memory (DDR5, LPDDR5), Flash Memory, Ethernet (400G), MIPI, PCIe (5.0), SAS, SATA, USB (4.0/3.x, Type-C). For a complete list of Verification IP and Test Suites, visit www.synopsys.com/vip.
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