Posted by VIP Experts on June 4, 2019
PCI-SIG recently announced the New PCI Express® 5.0 Specification, reaching 32GT/s transfer rates while maintaining low power and backward compatibility with previous technology generations. Aligned with this, Synopsys also announced the collaboration of its Design and Verification Solutions with Astera Labs to Develop Industry’s First PCIe 5.0 Retimer SoC. Emerging applications like AI, cloud, data center, and 5G have been driving the exponential increase in bandwidth requirements and PCIe has evolved to meet these increasing requirements.
In this blog, we discuss the new features in PCIe 5.0 and how the standard has evolved over the years.
PCIe protocol has rapidly evolved over the last 15+ years, from a raw bit rate of 2.5GT/s in 2002 with Gen1, to today’s 32GT/s with this latest PCIe 5.0. The adoption of the PCI Express from desktop computing to cloud, growing demand for increased throughput, reduced latency, footprint, and power have been driving the innovation in the PCIe standard.
Significant new features have been added to PCIe 5.0, such as new Equalization Options and Alternate Protocol Negotiation (APN), to meet the system requirements with predictable and stable bandwidth, latency and power (see below).
Synopsys VIP and source code Test Suite for PCIe 5.0 has been adopted broadly across industry leaders working on next generation cloud, data center, 5G, and HPC designs since the initial conception of the specification. VIP capabilities and tests suites are enhanced and matured working with these leading PCIe Gen5 adopters to systematically mitigate their design implementation risk of the new features published in each specification draft (see below) .
Synopsys VIP delivers enhanced performance and verification productivity gains through its native SV/UVM implementation and native integration with Synopsys VCS and Verdi Protocol Analyzer. Synopsys VIP is delivered with built-in functional coverage and source code Gen 5 Test Suite to accelerate the verification closure and achieve tape-out of first-pass quality designs.
Join Synopsys PCIe experts at PCI-SIG Developers Conference on June 18-19, 2019 at the Santa Clara Convention Center. Visit the Synopsys booth to see the complete DesignWare Controller, PHY, and Verification IP Solution and to network with experts. Synopsys will also provide several demos covering the PCIe 5.0 Integrated IP Core, PHY, and Verification IP and source code Test Suites.
For more information on Synopsys VIP, please visit http://synopsys.com/vip.
Stay tuned for upcoming PCIe blogs, where we will go through each of the new features in detail as well as the corresponding verification challenges and solutions. Meanwhile read our recent blogs on PIPE 5.1.1 for PCIe 5.0, DP 1.4, USB 3.2, SATA, and Future Protocols.
Authored by Sumit Dalal.