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DDR5/4/3/2: How Memory Density and Speed Increased with each Generation of DDR

The key features driving future memories are memory density, speed, lower operating voltage, and faster access. DDR5 supports memory density from 8Gb to 64Gb combined with a wide range of data rate from 3200 MT/s to 6400 MT/s.  The operating voltage of DDR5 is further reduced from 1.2V of DDR4 to 1.1V.

The speed that DDR5 now offers is 16x faster than the first ever SDRAM. This is achieved through a significant jump in speed and density, increased in each generation of DDR. In this blog, we will discuss the evolution of different DRAM memories, from SDRAM to the latest DDR5. To know more about the latest memory specifications, read our recent blog – Industry’s First LPDDR5 IP & VIP Solution Extending Leadership in DDR5/LPDDR5.

DRAM produced from the early 1970s to mid-1990s used an asynchronous interface in which input control signals have a direct effect on internal functions. SDRAM, introduced in 1993, provided a synchronous interface, whereby changes on control inputs are recognized after a rising edge of its clock input. It supported a memory density of 512Mb. Following SDRAM, a series of DDR arrived in the market, each one having some new features and increase in memory density. Now, the next generation DDR5 is here to ensure higher memory density and many new features at lower power consumption and higher speed.

SDRAM (Synchronous Dynamic Random Access Memory): 

SDRAM is dynamic random access memory that is synchronized with the clock speed of CPU. SDRAM also stands for SDR SDRAM (Single Data Rate SDRAM). Single Data Rate means that SDR SDRAM can only read/write one beat of data in a clock cycle. It is required to wait for the completion of a command before transferring next read/write operation. SDR speed varies from 66 MHz to 133 MHz.

DDR (Double Data Rate SDRAM):

DDR SDRAM is a double data rate synchronous dynamic random access memory. It achieves the double data bandwidth without increasing the clock frequency by transferring data on both rising and falling edges of the clock signal. Prefetch buffer size is 2n (two data words per memory access) which is double of SDR SDRAM prefetch buffer size. DDR memories transfer n bits of data per clock cycle from the memory array to the memory internal I/O buffer. This is called n-bit prefetch.

DDR2 (Double Data Rate Second Generation SDRAM):

Similar to DDR1, DDR2 also transfers data at twice the clock speed (transferring data on the rising and falling edges of the clock signal). Also, the internal clock runs at half the speed of the data bus leading to higher bus speed and lower power. All the above factors help DDR2-SDRAM to achieve four data transfers per internal clock cycle. The prefetch buffer of DDR2 is 4 bit (double of DDR SDRAM).  The data rate of DDR2 is 400MT/s to 800 MT/s.

DDR3 (Double Data Rate Third Generation SDRAM):

DDR3 transfers data at twice the rate of DDR2 SDRAM enabling higher bandwidth and peak data rates. Two new features are also added, Automatic Self-Refresh and Self Refresh Temperature Range, leading memory to control the refresh rates according to the temperature variation. It’s prefetch buffer width is 8 bit.

DDR4 (Double Data Rate Fourth Generation SDRAM):

DDR4 is able to achieve even higher speed and efficiency, though keeping the prefetch buffer size 8n, same as DDR3. The higher bandwidth is achieved by sending more read/write commands per second. DDR4 standard divides the DRAM banks into two or four selectable bank groups, where transfers to different bank groups can be done faster. Operating voltage of DDR4 is also less compared to DDR3. Few new features are also added, such as DBI (Data Bus Inversion), CRC (Cyclic Redundancy Check) and CA parity. These new features enhance DDR4 memory’s signal integrity and improve the stability of data transmission/access.

DDR5(Double Data Rate Fifth Generation SDRAM):

The DDR5 SDRAM achieves higher speed by using 16n prefetch buffer. DDR5 divides the DRAM banks into two or four or eight selectable bank groups compared to DDR4 which uses up to 4 bank groups. Some new features are also added:

  • Write pattern command – It saves power by not sending the data across the bus.
  • Enhanced PDA: Using the CA interface as the only method for per DRAM addressability by having unique PDA enum id assigned to each DRAM. As a result, subsequent commands need not to use the DQ signals to decide which DRAM is selected for the command.
  • Write leveling two types of trainings – External WL training for cycle alignment (like DDR4), Internal WL training for phase alignment.
  • Support of various training like CA training, CS training etc.

Table below lists the basic differences among DDR generations:

With every new generation of DDR, the memory density and speed is increasing significantly.

Synopsys is engaged with the early adopters of LPDDR5, DDR5 and DFI 5.0 VIPs. VIP for DDR4/3/2 and LPDDR4/3/2 have also been deployed successfully across industry leaders and market makers. For more information, please visit http://synopsys.com/vip. Stay tuned for upcoming blogs on next generation DRAM and Flash memory technologies, and also read our recent memory VIP blogs: