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Industry’s First LPDDR5 IP & VIP Solution Extending Leadership in DDR5/LPDDR5

Synopsys recently announced the fastest, and most power efficient DDR5 and LPDDR5 IP solutions. Industry’s first LPDDR5 controller, PHY, and verification IP solution supports data rates up to 6400 Mbps with up to 40% less area than previous generations. The LPDDR5 IP provides significant area and power savings for mobile and automotive SoCs with its dual-channel memory interface option that shares common circuitry between independent channels. The DesignWare DDR5 IP, operating at up to 4800 Mbps data rates, can interface with multiple DIMMs per channel up to 80 bits wide, delivering the fastest DDR memory interface solution for artificial intelligence (AI) and data center system-on-chips (SoCs). The DDR5 and LPDDR5 controller and PHY seamlessly interoperate via the latest DFI 5.0 interface.

Synopsys offering for a complete next generation memory verification solution includes VIP for DDR5, LPDDR5, DFI 5.0, HBM, GDDR6, and NVDIMM-P/N; and native integrations and optimizations with VCS and Verdi. While the Synopsys IP provide fastest memory interfaces, reducing area and power; Verification IP also provide the fastest verification solution, reducing time and effort required to tape-out first-pass quality designs. The complete design and verification solution can save valuable man hours and enable design teams to meet tight schedules and time-to-market requirements. In our previous memory blog, we discussed the new LPDDR5 features based on our collaborations with memory vendors and early adopters of Synopsys VIP over last 2 years –  LPDDR5: Enhancements in Bandwidth, Reliability, and Power for IoT, AI, and Image Processing.  In this blog and upcoming Memory VIP blogs, we will see, how Synopsys Memory IP, VIP, VCS, and Verdi provide a complete solution and enhances productivity multi-fold.

Synopsys VIP stays ahead of the curve by collaborating with leading memory vendors and providing access to latest vendor specifications and memory models. This enables Synopsys VIP to provide the most up-to-date and fully qualified verification components including vendor part numbers, timing and protocol checks, and functional coverage.

Here’s a list of the top 10 reasons to select Synopsys Memory VIP. These features enhance productivity multi-fold, making Synopsys memory verification solutions the fastest, reducing time and effort required to tape-out first-pass quality designs. We will go into details of each of the 10 reasons in our next blog.

  1. SoC and memory design leaders adopting next generation Synopsys memory VIP
  2. Out of the box support for all possible JEDEC part numbers at run-time
  3. Run time vendor part selection and randomization
  4. On-the-fly UDIMM/RDIMM/LRDIMM configurations
  5. Modelling and randomization of real world signal delays to mimic process, voltage, and temperature variations
  6. Advanced memory verification and modelling features
  7. Comprehensive functional and timing coverage and verification plan
  8. Native integration with Verdi® protocol and memory aware debug
  9. Native integration with Verdi® Performance Analyzer with performance metrics for complex design calculations
  10. Native SystemVerilog/UVM architecture

For more information on Synopsys IP and VIP, please visit:
https://www.synopsys.com/designware-ip.html
http://synopsys.com/vip

Stay tuned for our next blog going into details of each of the 10 reasons listed above. In the meantime, checkout our other recent memory VIP blogs and articles:

Authored by Ankur Jain.