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How DFI 5.0 Ensures Higher Performance in DDR5/LPDDR5 Systems?

The growth of datacenter, storage, automotive and other emerging market applications is driving the development of next-generation memory technologies – DDR5, LPDDR5. Like their predecessors, the latest memory technologies also use DFI, a standard interface between memory controller and PHY, to reduce the integration cost and increase performance and data throughput efficiency. DFI also has evolved along with the memory technologies, and next generation DFI 5.0 is here to ensure higher performance in the systems using DDR5/LPDDR5. In this blog, we will discuss the new features of DFI 5.0 specification.

DFI defines signals, timing, and functionality required for efficient communication across the interface. The specification is developed for design of both memory controller and PHY, but does not place any restrictions on how the memory controller interfaces to the system design, or how the PHY interfaces to the DRAM devices.

In DFI 5.0, training mode has been completely transformed to be a PHY-independent training mode, there by the PHY trains the memory interface without involving the controller. Geardown mode also has been extended to 2N mode. A new signal dfi_2n_mode has also been added to support this behavior. There are other significant improvements in DFI 5.0 to reduce power consumption, and improve interoperability & interface communication.

DFI changes specific to LPDDR5

FSP (Frequency Set Point)

LPDDR4/5 added two physical sets of register spaces, FSP0 and FSP1, to switch between two different operating frequencies without retraining. A new signal dfi_freq_fsp has been added in DFI status interface to indicate operating FSP for the system. This signal should change only at initialization or during a DFI frequency change operation. A new parameter dfifspx_freq has been added (where x is defined by the number of FSPs supported in the DRAM) which defines the frequency for each FSP. This is an encoded value as defined by the dfi_frequency signal and the phyfreq_range programmable parameter.

WCK (Write Clock)

An LPDDR5 SDRAM utilizes two types of clock with different frequency. The frequency of WCK is four times or twice higher than the command clock. Signals are defined in DFI 5.0 interface to control the WCK synchronization sequence – turning the WCK on, the toggle modes, the static states, and turning the WCK off.  The signals are sent from the controller to the PHY data slices and are phased signals defined by the data interface clock frequency ratio. The dfi_wck_en signal defines when the clock is enabled or disabled. The dfi_wck_toggle signal communicates the states of the WCK: STATIC_LOW, STATIC_HIGH, TOGGLE and FAST_TOGGLE.

Changes in DFI interface for DDR5/LPDDR5

Message Interface

The MC to PHY message interface handles the transmission of encoded messages from MC to PHY; it includes signals and timing parameters. In a DDR memory subsystem, the memory subsystem functions may be supported in the controller, or PHY, or both. In some instances, a function executed by the controller may result in the need to send a message to PHY. The messaging includes both pre-defined messages and device-specific messages. The controller and PHY should support the same encodings.

In nutshell, DFI 5.0 has new interfaces like WCK to increase speed at which data is sampled, and support for multiple frequency sets resulting in lossless communication to DRAM. It has also added message interface to improve communication between MC and PHY. Other interface changes include enhancements to reduce power, PHY-independent boot sequence, and expanding frequency change support etc.

Synopsys is engaged with the early adopters of LPDDR5, DDR5 and DFI 5.0 VIPs. For more information, please visit http://synopsys.com/vip. Stay tuned for upcoming blogs on next generation DRAM and Flash memory technologies, and also read our recent memory VIP blogs:

Authored by Shivani Bansal.

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