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High Capacity and High Performance Flash Memory

High speed memory interface is a critical component to support high speed data in applications like personal computers, mobile phones, and digital cameras.  These applications require a high capacity and high performance NAND flash memory, and Toggle2NAND is one of the most suitable NAND interfaces.

Toggle2NAND makes use of Double Data Rate (DDR) without a clock, yet it is compatible with the functions and commands supported in conventional SDR NAND. While providing high data transfer rate, power saving is also achieved with separated DQ voltage. Toggle2NAND supports speed up to 200 MHz (400 Mbps), more than 10x faster than the data transfer rate offered by SDR NAND (40 Mbps).

Next generation Toggle3NAND supports the interface speed of up to 400 MHz (800 Mbps), which is 2x faster than the data transfer rate offered by Toggle2NAND Flash Memory (400 Mbps).

In our previous memory blog, we discussed the new LPDDR5 features based on our understanding from collaboration with memory vendors and early adopters of Synopsys VIP over last 2 years – LPDDR5: Enhancements in Bandwidth, Reliability, and Power for IoT, AI, and Image Processing. In this blog, we will talk about Toggle3Nand/Toggle2NAND basic operations, and how it delivers higher performance at lower power consumption.

DQS Signaling
Toggle2NAND utilizes the bidirectional DQS signaling, to transfer data at high speeds. DQS signal behaves as a clock and is used only while data is transferred, resulting in optimal power consumption.  In the Toggle2NAND addressing scheme two address types are used – column address and row address. The column address is used to access bytes within a page (i.e. the column address is the byte offset into the page). The least significant bit of the column address should always be zero (i.e. an even number of bytes are always transferred).

The plane address is comprised of the lowest order bits of the block address as shown in the figure above. The plane address is used when performing a multi-plane operation on a LUN. This addressing scheme provides a higher data rate, enabling multiple operations in same window.

Toggle2NAND Page Read Operation
Here is a typical example of the read data from memory device.  The read data is sent on each edge of DQS signal, providing DDR transfers. Below is the Verdi snapshot and order of the page read operation:

  • The controller sends the command (00h) a PAGE_READ command (used to read device data)
  • The command (00h) is followed by the address ({column address}, {row address})
  • The second opcode of PAGE_READ command (30h) comes next
  • The device goes busy for read busy time (tr) by de-asserting RB signal
  • The end of the operation is signaled when data starts coming on each DQS edge once RB toggles from low to high

Toggle2NAND Page Program Operation
Let’s now look at the page program operation inside the device memory.  Below is the Verdi snapshot and order of the page program operation:

  • The controller sends the command (80h) a PAGE_PROGRAM command (used to write device data)
  • The command (80h) is followed by the address ({column address}, {row address})
  • The controller starts sending data on each DQS edges
  • The second opcode of PAGE_PROGRAM command (10h) is shown
  • The device goes busy for program busy time (tprog) by de-asserting RB signal
  • Once data is written into the end memory device toggles RB from low to high

NAND Flash Types
There are three main types of NAND flash technology:

  1. Single-level cell (SLC): Stores 1 bit per cell, offers the highest endurance
  2. Multi-level cell (MLC): Stores 2 bits per cell, provides medium endurance
  3. Triple-level cell (TLC): Stores 3 bits per cell, offers lowest endurance

Flash memory manufacturers have improved the endurance and reliability of MLC and TLC flash drives through error correction code algorithms. Toggle2NAND supports all three types of technologies.

Toggle2NAND provides higher data rates using the double data rate signaling for data transfer to memory. Toggle2NAND devices support simultaneous read (i.e. dual bus support). It also supports program and erase operations on multiple die-on-the-same-chip, and the multi LUN transactions. These features increase the throughput of the devices. Next generation Toggle3NAND further doubles the interface speed up to 400 MHz (800 Mbps).

For more information on Synopsys memory VIP, please visit http://synopsys.com/vip. Stay tuned for our upcoming blogs on DRAM and Flash memory technologies. Our recent blogs on next generation DRAM and Flash memory technologies: –

Authored by Amit Tyagi.