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Arm AMBA 5 AHB5: Accelerating the Embedded and IoT World

Ever since Arm released the Arm® AMBA® 5 AHB5 protocol specifications, questions have arisen among users in the design and verification community—”Why AHB5?”, “What is new in AHB5?” etc. This post initiates a short series of blogs in which we will address these questions and introduce the new features of AMBA 5 AHB5.

Why AMBA 5 AHB5?

AMBA 5 AHB5 (Advanced High Performance Bus) is a bus interface protocol, which will most widely be used with Arm Cortex-M processors for embedded designs and low latency SoCs, for IoT and embedded applications. The new features of AHB5 build upon the previous generation AHB-Lite protocol, aligning it with the AXI4 protocol. AHB5 also extends the TrustZone security foundation from the processor to the entire system. This enables a unified security solution inclusive of AXI and AHB systems, easing the SoC integration process.

 

What is new in AMBA 5 AHB5?

The new features in AMBA 5 AHB5 that are aligned with the AMBA AXI4 protocol include:

  • Secure/non-secure signaling in address phase to indicate secure or non-secure transactions
  • Extended memory types to support more complex systems
  • Exclusive transfers that support semaphore-type operations

AMBA 5 AHB5 also provides further improvements on the AHB-Lite protocol, as it becomes more widely adopted:

  • Multiple slave select for area efficiency
  • Single-copy and multi-copy atomicity enabling scaling to multiple cores
  • User signaling allowing for user extensions

New interface signals have been added to the existing AHB-Lite interface, to support features like secure/non-secure and exclusive transfers. Supported/unsupported properties for new features are also defined, making it backward compatible with existing AHB-Lite protocol. AHB supports both big-endian and little-endian systems. AHB5 adds endian property to define which form of big-endian data access is supported – BE8 (Byte-invariant big-endian) and BE32 (Word-invariant big-endian). The 4-bit HPROT signal is also extended to 7-bit to support extended memory types.

Synopsys VIP for AHB5

The new features and complexity of the AHB5 protocol pose a significant verification challenge. Synopsys VIP for AMBA AHB supports AHB5 along with AHB3-Lite and AHB2 specifications. Users can simply change a few configuration attributes and signal connections to switch to different AHB modes. The expanded capabilities of Synopsys VIP include system level test suites, a system monitor, Verdi integrated protocol-aware debug, and performance analysis. The system-level capabilities of Synopsys VIP enable SoC teams to further accelerate time-to-first-test and improve overall verification productivity.

AMBA 5 AHB5 features targeting area-efficiency, low-latency, and low-power are ideal for embedded and IoT solutions. The next post in this series will discuss the AHB5 new features in greater detail and how Synopsys VIP can be leveraged. Stay tuned as we explore the world of AMBA 5 AHB5!

Read our previous blog on AMBA – Verification Automation Solutions for Arm AMBA Coherent Interconnects

To know more about Synopsys AMBA and other VIPs please visit   http://synopsys.com/vip.