In June 2017, PCI-SIG announced the new PCI Express 5.0 specification, at the PCI-SIG DevCon. The new version of the specification doubled bit rate to 32GT/s per lane providing about 128GB/s bandwidth for a x16 Link (16 lanes). The chart below provides a comparison of bit-rate and bandwidth for the different PCIe Generations.
The PCIe Physical Layer will utilize the 128b/130b encoding when operating at 32.0 GT/s data rate. This new data rate will be backwards compatible with the prior data rates. The PCIe Link will be trained to L0 state with 2.5 GT/s, like before and then move to the higher data rate(s). The TS1 and TS2 Ordered Sets in 8b/10b encoding as well as 128b/130b encoding are enhanced to include the 32.0 GT/s data rate support. The equalization phases are similar to previous generation 8.0 GT/s and 16.0 GT/s data rates. After initial Link training to L0 in 2.5 GT/s, the Link will perform equalization at 8.0 GT/s, followed by 16.0 GT/s and 32.0 GT/s equalizations sequentially. It is an optional feature to skip (or reorder) equalization at lower data rates when supporting 32.0 GT/s. In addition to this option to skip equalization, alternate protocols will be negotiated through Link training.
The ElEOS Ordered Set in 128b/130b encoding is extended to include longer run length of 0s and 1s. At 32.0 GT/s, another 19 sets of compliance patterns with various presets are added. A new extended capability structure and several register fields are added to house the 32.0 GT/s data rate. The Lane Margining at Receiver and Retimer support is not expected to change for 32.0 GT/s data rate.
Synopsys is engaged with the early adopters of PCIe Gen5 Verification IP and testsuite, based on version 0.5 of the specification. PCIe Gen5 VIP and testsuite are available as part of the 2017.12 release of VC VIP product. For more information on Synopsys PCIe Gen5 and other VIP, please visit: