Higher Mobile Storage Performance at Lower System Cost

Higher storage performance at a lower cost can create a bottleneck in the design of storage devices.  In order to achieve higher performance, devices must use on chip DRAM, which adds to the overall cost. This is where Unified Memory Extension (UME), a JEDEC specification, comes into the picture. It is defined as extension to the JEDEC UFS (Universal Flash Storage) specification. JEDEC UFS device uses NAND flash technology for data storage. Unified Memory (UM) allows users to use part of the host memory as the device’s internal memory. Since the host memory is already available in large capacities, this mechanism provides a much bigger space for the device to use as a Write Buffer (WB) cache or to store information such as Logical to Physical (L2P) address translation tables. The UM area is physically located on the host side but ultimately belongs to the device, thereby replacing the device-integrated RAM, and reducing overall cost. Large space availability means the device can store larger amounts of WB of L2P table information resulting in higher storage performance.

A UFS device uses the extended UFS Transport Protocol (UTP) definition to communicate with the UFS host. Whenever data in the UM area is to be overridden by the device, it will be written to the non-volatile memory through a WB flush operation, as shown below.

The UM may contain most of the caches listed below. These caches will be updated by the device as needed so that both the host and the device have the same data.

1. L2P table cache
2. WB cache
3. L2P table cache tag
4. WB cache tag

Unified Memory Initialization and Configuration

The available UM area space is communicated to the device by programing the dUMAreaSize attribute. It will also communicate the supported number of outstanding UM requests through the bMaxUMPIURequests attribute, improving performance by processing multiple UM requests simultaneously. The host enables the UM operation by setting the fUM flag and polls the flag until the device clears it.

L2P Table Operation

The device will read the L2P table cache tag present on the host side and compare it to its own copy. If a cache hit occurs, the device will read the L2P table cache line else it will update the host buffers with a new L2P table cache tag and line as shown below. This is required only when the device side L2P cache is updated.

Unified Memory Read/Write Operations

When the host sends a write request, the device will initiate the L2P cache operation, if applicable. Then it will read the WB tag for checking. If a cache collision and dirty occurs, the WB line should be flushed before the SCSI data phase (copy from System Memory to UM). When host sends read request, device will initiate L2P cache operation, if applicable. Then it will read the WB tag for checking. In case of cache hit, it will request to copy from UM to system memory, or else the device will send the data to the host through “Data in” UPIU (UFS Protocol Information Unit).

Advantages of Unified Memory

• The access speed of UM is much higher than a non-volatile memory. While accessing L2P information, if there is a cache miss the non-UM approach requires fetching this from a non-volatile memory. The UME approach instead can provide this from the system memory, improving L2P table access times tenfold.
• UM provides more buffers than device-integrated RAM; therefore, more L2P information can be stored, reducing the cache miss ratio.

Disadvantages of Unified Memory

• The host is maintaining two copies of memory instead of system memory pointing to the UM memory.
• Latency for UM access may be higher and more volatile compared to the device-integrated RAM; however, systems may strike a tradeoff by using smaller RAM in addition to UM area usage. This can reduce cost while retaining a high response time for some of the read/write accesses.

UM is offering space to store large chunks of WB and L2P data by which higher performance can be achieved. Hence there is no need for large amount of device-integrated RAM which helps in reducing system cost and read latency.

Recent UFS blogs

How to Address the Top 7 JEDEC-UFS Stack Verification Challenges Using Test Suites

UFS – Faster and Secured Flash Storage

Stay tuned for upcoming blogs on UFS and other flash memory technologies. Synopsys provides next generation native SV/UVM based VIP and Test Suite for complete UFS stack verification and other flash memories. To know more about our VIPs please visit http://synopsys.com/vip.

Authored by Manoj Sharma Tanikella