VIP Central

 

Verification Automation Solutions for Arm AMBA Coherent Interconnects

Arm TechCon 2017 took place at Santa Clara on 24-26th Oct, 2017. This year, Synopsys’ Arm® AMBA® protocol experts were on hand to demonstrate our verification automation solutions for Arm AMBA Coherent Interconnects. Synopsys Auto SoC Testbench generation solution enables easy and quick integration and configuration of hundreds of coherent and non-coherent AMBA ports and corresponding VIP instances. Our experts also introduced our AMBA AutoPerformance solution to generate AMBA(CHI/ACE/AXI) interconnect performance verification stimulus. The AutoPerformance solution, based on Arm traffic profile specification, enables user to define traffic profiles for measurement of performance metrics like throughput, latency etc., and the stimulus is driven by VIP for AMBA (CHI/ACE/AXI).

In addition, our design and verification experts presented a tutorial on Functional and Performance Validation for Arm Cache Coherent Interconnects. The tutorial outlined a flow to perform functional and performance validation for Arm cache coherent interconnect networks, based on the Arm CoreLink CMN-600 mesh, using our solutions for automatic SoC Testbench generation, performance validation using Arm traffic profile specification, AMBA Verification IP and Test Suites, VCS simulator and Verdi Performance Analyzer.

Synopsys has a comprehensive verification solution for Arm AMBA protocols and interconnects covering the latest specifications. Synopsys VIP is implemented in 100% native System Verilog and UVM to enable ease-of-use, ease-of integration and high performance. VIP is natively integrated with VCS, Verdi® Protocol Analyzer and Performance Analyzer, and provides configurable interconnect model, system level monitor, checkers, and performance metrics.  Complete, self-contained, and design-proven source code test suites, written in System Verilog and UVM, are also available for comprehensive protocol testing and coverage. Test suites are provided as source code enabling users to easily customize or extend the environments to include unique application-specific tests or corner-case scenarios.

Synopsys recently announced the availability of Verification IP and source code Test Suite for ARM AMBA 5 CHI (Coherent Hub Interface) Issue B.

The verification automation soultions enable users to quickly integrate and configure the complex interconnects and generate performance verification stimulus, resulting in multi-fold productivity gains. For more information on the verification automation solutions, please request here.

Authored by Ankur Jain.