Posted by VIP Experts on October 24, 2017
MIPI Camera Serial Interface (CSI-2) is widely used as a camera interface in the mobile industry. MIPI Alliance is constantly working towards providing a solution to cater the increasing demand for higher-bandwidth and high-definition video like 1080p, 4K, and 8K. The MIPI Working Group released CSI-2 v2.0 to target emerging imaging and vision applications. It has extended the usages of CSI-2 to IoT, wearable devices, drones, Virtual Reality (VR) and Augmented Reality (AR), and automotive systems.
CSI2 is a high-bandwidth interface between a camera and a host processor. Data is transmitted using differential signals using a clock lane. The physical layer, used with CSI-2, can be D-PHY or C-PHY based on the requirements. Performance using both physical layers are scalable, which can deliver data-bandwidth up to 8 Gbps per lane or up to 24 Gbps in a three lane C-PHY system. Below figure shows the topology which can be used by a CSI-2 camera sensor and an application processor with D-PHY or C-PHY as the physical layer.
CSI-2 v2.0 supports D-PHY v2.0 and C-PHY v2.1. The following sections are a deep dive into various new features that have emerged in the latest specifications.
– Lane Scalability: A CSI-2 D-PHY system can have multiple data lanes, which is scalable, and one clock lane.
– Support for 16 interleaved virtual channels on D-PHY link
– Support for up to 32 virtual channels on C-PHY link
– 6 Bit Error Correction Code for error detection and correction on D-PHY link
– RAW16 and RAW20 data
– Data Scrambling: The purpose is to mitigate the effects of EMI and RF self-interference by spreading the information transmission energy of the link over a possibly larger frequency band, using a data randomization technique.
– Latency Reduction and Transport Efficiency(LRTE): LRTE is an optional CSI-2 feature that facilitates optimal transport of data to support several emerging imaging applications. LRTE has two parts, Inter-packet Latency Reduction (ILR) and Enhanced Transport Efficiency (ETE).
CSI-2 v2.0 with D-PHY v2.1:
– High data rates above 4.5Gbps which will allow data streaming at very high bandwidths
– The D-PHY provides an Alternate Low Power State (ALPS) using Low Voltage Low Power Signaling (LVLP). Use of LVLP can help alleviate current leakage and electrical overstress issues with image sensors and application processors.
CSI-2 v2.0 with C-PHY v1.2:
– The C-PHY provides ALPS signaling using LVLP signaling or Alternate Low Power (ALP) Embedded Codes, which may optionally replace the legacy Low Power State (LPS).
– Use of ALPS can help alleviate current leakage and electrical overstress issues with image sensors and applications processors. ALPS using the ALP Embedded Codes can also help achieve longer reach for CSI-2 imaging interface channels before re-drivers and re-timers become necessary.
New features of CSI-2 v2.0 are enabling usages of CSI-2 in the emerging sectors influenced by mobility, vision, and video. Synopsys recently announced the Industry’s First Verification IP and Test Suites for MIPI CSI-2 v2.0 and PHY Specifications. For more information on Synopsys CSI-2 and other VIPs, please visit: www.synopsys.com/vip.
Authored by Dipesh Handa
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