Posted by Ankur Jain on October 10, 2017
USB has literally become universal and present in every device ranging from smart phones and personal computers, IoT and wearables, storage and networking, consumer electronics and gaming consoles, automotive and many other emerging verticals. The success of USB can be attributed to innovation with each new generation—the capability to transfer data as well as supply power for charging devices and ease-of-use with a variety of connectors and form factors.
USB Implementers Forum (USB-IF) recently announced the publication of the USB 3.2 specification, while Synopsys just announced the availability of the industry’s first VIP and UVM source code Test Suite for USB 3.2.
USB 3.2 enables new hosts and devices with USB Type-C™ to be designed as multi-lane solutions. Allowing up to two lanes of 5 Gbps or two lanes of 10 Gbps operation, doubles the data rate over the existing USB Type-C cables. It also supports re-timer enhancements. Below is a list of key enhancements in USB 3.2 as announced by USB-IF:
USB has been one of the primary protocols driving the digital revolution over the years. It started with requiring universal replacement of a variety of serial and parallel ports to connect peripherals in the mid-90’s, and was whole heartedly adopted by PC manufactures. USB then became the popular interface for flash based storage devices. The speed and power supply was increased multifold, driving ubiquitous use of USB. The USB Power Delivery (PD) specification took power supply to the next level by delivering power ranging from 60W (3A @ 20V) to 100W (5A @ 20C) over varied cable profiles from Type-C unmarked cables to Type-C electronically marked cables. In mid-2014, the USB Type-C standard was announced, which provided the thinner, reversible connector and ever evolving ecosystem of new platforms like MHL, DisplayPort, HDMI, and Thunderbolt over Type-C. Continuing the innovation, USB 3.2 further enhances the USB capabilities with support for multi-lane solutions.
Synopsys was first-in-industry for USB PD 3.0 VIP, and continues to be first-in-industry with USB 3.2 VIP. Currently, Synopsys is the only provider of complete support for USB verification including the following USB specifications and modes:
– USB 3.2, 3.1, 3.0, 2.0
– On-The-Go 3.0, 2.0
– USB Power Delivery 3.0, 2.0
– Type-C subsystem supporting USB, USB PD, and DisplayPort over Type-C
– UVM source code Test Suite
– Host, device, and hub emulation
– Option of emulating cable plug within a single agent
Synopsys’ complete verification solution for USB enables customers to achieve accelerated verification closure of the latest USB IP, subsystem and SoC designs. Below is a summary of the advanced verification features of VIP:
– Native SystemVerilog/UVM based next generation architecture
– Comprehensive source code Test Suites
– Native integration with Verdi® Protocol Analyzer
– Built-in coverage and verification plans to speed up verification coverage closure
– Built-in protocol checks for robust verification
The UVM source code Test Suite provides an easy to integrate testbench and comprehensive set of tests. The testbench for a host DUT connected to a device VIP provides a host driver to translate data objects to DUT specific API sequences. There is also an xHCI driver for generic xHCI register model and memory operations. For example, to create a command TRB and write it to a command ring, ring the command doorbell and watch the command completion event TRB. The testbench for a device DUT connected to a host VIP provides a device driver to translate data objects to DUT specific API sequences.
Synopsys USB verification solutions are being adopted rapidly and in production by many customers. Read more about Adoption of Synopsys USB Type-C Subsystem Verification Solution by ASIX. For more information on Synopsys VIP for USB and verification subsystem solution for USB Type-C, please visit: www.synopsys.com/vip.
Recent USB blogs:
A global team of protocol experts that share their insights and technical expertise in the areas of Automotive, DRAM and Flash Memories, Storage, Display, MIPI, AMBA, Ethernet, PCIe, USB and many other bus and interface protocols. This comprehensive team participates in standards committees and will provide the latest information and updates as it relates to your future design considerations.