Posted by VIP Experts on September 20, 2017
‘Big Data’, ‘IoT’, ‘Mobile’, ‘Networking’ and ‘Storage’ applications are the key drivers for next generation high-performance systems. To meet the bandwidth requirement of the emerging applications, it was required to either increase the lane width or speed. Increasing the lane width isn’t cost effective and thus increasing speed is the best viable option. PCIe 4.0 has doubled the per lane throughput to 16GT/s, compared to 8GT/s for PCIe 3.0, delivering higher performance without increasing the lane width.
PCIe 4.0 architecture is backward compatible to previous generations of PCIe. Devices designed for previous generations will still operate correctly with the new technology. The figure below shows the evolution of PCIe specifications.
The PCIe 4.0 specification has multiple draft versions, incremental features have been added and existing features have been modified in each of the draft versions. Some of the earlier ECNs such as re-timer, DVSEC, PASID-ATS have also been added/applied to the PCIe 4.0 specification. The following list summarizes the newly added/changed features for PCIe 4.0:-
PCISIG Work Group has already announced PCIe 5.0 at the recently held PCISIG DevCon 2017. The PCIe 5.0 specifications will further increase the speed to 32 GT/s. The committee has shared that many of the PCIe 4.0 features will be reused in PCIe 5.0 with minor changes to incorporate the speed change. Below is a list of expected features in PCIe 5.0:
Synopsys VC VIP for PCIe supports all the new PCIe 4.0 features. The VIP provides robust 4.0 checkers that flag spec violation issues to identify bugs early in the design cycle. To learn more about Synopsys PCIe VIP and Test Suites, please visit http://synopsys.com/vip.
The upcoming PCIe blog will expand further on PCIe 4.0 features, so stay tuned.
Authored by Mukul Dawar.
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