Posted by VIP Experts on August 16, 2017
SPI interface is emerging as a popular choice in automotive applications ranging from sensors, display console, navigation systems, booting through SPI Flash and many more. SPI low pin count and configurable clock rate facilitate the requirements of the emerging automotive applications.
Synchronous Serial Peripheral bus (SPI) allows synchronous serial communication between a controller and peripheral devices. It enables full duplex or half duplex communication with continuous streaming of data communicated between master (controller) and slave (peripheral devices). It can be configured in multiple architectures ranging from single master-single slave to multi master-multi slave systems. The master will always be the controller of bus activity on the interface between the connecting components. The serial protocol supports a low pin count interface that consists of Chip Select, Clock, and Data out from controller to peripheral device and Data into controller pins from peripheral device. The low pin count interface based on selected configuration supports various vendor specific modes mentioned below.
Flavors of SPI
Motorola Serial Peripheral Interface (SPI)
Serial Peripheral Interface (SPI), developed by Motorola, allows duplex communication on a four-wire interface with distinctive features such as programmable serial clock polarity and phase.
Texas Instruments Synchronous Serial Protocol (SSP)
Synchronous Serial Protocol (SSP), developed by Texas Instruments, allows continuous streaming of data transfer by asserting frame indicators. It is a four-wire interface, with slave select also used as next frame indicator for continuous data stream.
National Semiconductor Microwire (UWIRE)
Microwire (UWIRE) or popularly known as 3 wire interface, developed by National Semiconductor, allows half-duplex communication between devices. Data communication either consists of control word followed by continuous data stream (sequential mode) or stream of control word followed by data word (Non-sequential mode).
Synopsys VC VIP for SPI
Synopsys VC VIP for SPI provides coverage driven exhaustive directed and random sequences, and run time configurable options to select among multiple modes to cater to a wide range of industry requirements. The VIP, based on next-generation native System Verilog and UVM architecture, provides built in verification plans and coverage for accelerated verification closure. VIP also supports integrated Verdi® Protocol Analyzer for advanced debug capabilities.
VC VIP for SPI supports SPI serial bus as well as SPI Flash including Dual, Quad, and Octal lane based NAND/NOR Flash models for vendors like Micron, Cypress, Spansion, Macronix, Winbond, and ISSI etc. Stay tuned to this page for upcoming blogs on SPI Flash.
For more information on Synopsys VIP, please visit: www.synopsys.com/vip.
Authored by Kapil Rajpal.
A global team of protocol experts that share their insights and technical expertise in the areas of Automotive, DRAM and Flash Memories, Storage, Display, MIPI, AMBA, Ethernet, PCIe, USB and many other bus and interface protocols. This comprehensive team participates in standards committees and will provide the latest information and updates as it relates to your future design considerations.