Posted by Ankur Jain on August 2, 2017
Synopsys hosted the annual Verification Luncheon and Customer Panel – SoC Leaders Verify with Synopsys at DAC 2017 in Austin, Texas. The panel featured industry experts and executives from Intel, Qualcomm, AMD, NXP, and Wave Computing, and drove our main messages of innovation and technology leadership, in addition to collaborations with market makers. In case you missed it, this blog provides the highlights and video of the event.
The panel kicked off with a short presentation on the momentum of our Verification Continuum platform and our market strength/growth with hardware. We then provided an update on the latest verification technologies in VCS Fine-Grained Parallelism, Verdi, SpyGlass, and VC Formal. The opening presentation also highlighted new innovations in power analysis and low power verification such as our new PowerReplay product. It was followed-up by a presentation on the evolution of emulation leading to FPGA-based emulation and innovation in verification software, helping to drive performance up to 15MHz.
Intel spoke about their collaboration with Synopsys for development of static verification tools to enable higher quality of results and velocity of design. It was followed-up by a discussion on Qualcomm’s low power collaboration with Synopsys, to deliver end-to-end UPF verification and a low power coverage and testbench methodology. Wave Computing discussed how they are addressing the unique hardware and software verification challenges of silicon for machine learning using ZeBu. NXP shared how they leveraged ZeBu to perform full Linux stack and applications bring-up for the i.MX SoC in just 8 days after 1st silicon! Finally, AMD highlighted their collaboration with Synopsys to achieve a 10X emulation performance improvement while still managing to run their “Software Continuum” across many teams at AMD.
Verification IP Announcement at DAC:
As part of our decade-long mutual collaboration with ARM, we announced the availability of our Verification IP and source code test suite for ARM AMBA 5 CHI (Coherent Hub Interface) Issue B, which occurred concurrently with ARM’s announcement for AMBA 5 family of protocols. CHI Issue B VIP enables customers and partners to verify the latest coherent system designs with new enhancements for increased performance.
Synopsys VC Verification IP (VIP) provides verification engineers access to 90+ industry’s latest protocols, interfaces and memories required to verify their SoC designs. Deployed across thousands of projects, Synopsys VIP supports ARM® AMBA®, CCIX, Ethernet, MIPI®, PCIe®, USB, DRAM, and FLASH memory, automotive, display, storage, and other BUS/interface protocols. For a complete list of Verification IP and Test Suites, visit www.synopsys.com/vip
Authored by Ankur Jain.
A global team of protocol experts that share their insights and technical expertise in the areas of Automotive, DRAM and Flash Memories, Storage, Display, MIPI, AMBA, Ethernet, PCIe, USB and many other bus and interface protocols. This comprehensive team participates in standards committees and will provide the latest information and updates as it relates to your future design considerations.