Posted by VIP Experts on June 27, 2017
There was a time when coherent multi-processor systems were a niche technology with complex proprietary architectures. With ever increasing demand for performance, coherent systems with multiple processors and coherent accelerators are now being adopted rapidly across applications and market segments ranging from infrastructure networking and servers to storage and automotive. ARM® AMBA® 5 CHI provides the much needed standard architecture for coherent designs.
SoC leaders have adopted Synopsys VIP for CHI and other AMBA protocols for successful verification closure and tape out of coherent subsystems and interconnects. As a result of the pro-active collaboration with ARM to develop and prove VIP for CHI we have seen a rapid adoption of the CHI VIP and TestSuite.
ARM recently announced CHI Issue B as a part of the ARM AMBA 5 family of protocols, enhancing the standard architecture for next-generation coherent designs.
ARM AMBA 5 CHI Issue B provides following new features:
As part of our decade-long mutual collaboration with ARM, Synopsys announced the availability of our Verification IP and source code Test Suite for ARM AMBA 5 CHI (Coherent Hub Interface) Issue B, which occurred concurrently with ARM’s announcement.
CHI Issue B VIP enables customers and partners to verify the latest coherent system designs with new enhancements for increased performance. Below is a summary of advanced verification features of VIP:
To learn more about Synopsys VIP and Test Suites for CHI Issue B and other AMBA protocols, please visit http://synopsys.com/vip.
Authored by Ankur Jain.
A global team of protocol experts that share their insights and technical expertise in the areas of Automotive, DRAM and Flash Memories, Storage, Display, MIPI, AMBA, Ethernet, PCIe, USB and many other bus and interface protocols. This comprehensive team participates in standards committees and will provide the latest information and updates as it relates to your future design considerations.