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Is JESD204B A New Buzz Word In FPGA?

The JESD204B specification is the newer version published by JEDEC standard for data converters and logic devices. If you are working on high-speed data capture designs using an FPGA, you’ve would have heard the new buzz word, ‘JESD204B’. This newer version provides significant benefits over LVDS and CMOS interfaces, as it includes an easier layout and reduced pin-count. The JESD204B standard has a layered architecture, and is comprised of 3 layers beginning with Transport Layer at top, extending to Link Layer in middle and Physical layer at the bottom. Mirror Image is the structure at receiver side, with bottom up approach (Physical layer -> Link layer -> Transport layer). Each layer has a unique function to perform.

JESD204B Transmitter Flow
                                                                JESD204B Transmitter Flow

The transport layer maps conversion samples to and from framed non-scrambled octets.  The scrambling layers can optionally take those octets and scramble or descramble them in order to reduce EMI effects by spreading the spectral peaks.  Scrambling would be done in the transmitter and descrambling done in the receiver.  The data link layer is where the optionally scrambled octets are encoded to 10-bit characters.  This layer is also where control character generation or detection is done for lane alignment monitoring and maintenance.  The physical layer is the serializer/deserializer or (SERDES) layer responsible for transmitting or receiving the characters at line rate speeds. JESD204B protocol stack has seven functional blocks in the transmit path and seven functional blocks in the receive path, as shown in figure below.

JESD204B Protocol Stack
                                                                         JESD204B Protocol Stack

With JESD204B addressing data synchronization, it’s being adopted in automotive, medical imaging, radars, and other Mil-Aero and industrial applications. JESD204B is quickly gaining support from analog vendors who are thinking to interface high speed ADCs and DACs with programmable SOCs all of which are available with on-chip serial transceivers to take full advantage of the JESD204B serial bandwidth.

Synopsys provides 100% native SystemVerilog/UVM based VIP for JESD204A/B, with a comprehensive set of protocol, methodology, verification, and productivity features for accelerated verification closure. Each layer in VIP caters to a specific need, Transport Layer defines the mapping of data-> octets->frames and is summarized by the transport layer parameters. Link Layout primarily consists of definitions for 8b/10b encoding, Link Synchronization and Link Monitoring. Variety of link errors are detected and reported over the SYNC~ interface by this layer. To know more about Synopsys JESD204A/B and other protocol and memory VIPs please visit http://synopsys.com/vip.

You can also read our previous blog on JESD – JESD204B: New Alternative for High-Speed Data Acquisition up to 12.5Gbps.

Authored by Anika Malhotra.

 

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