AMBA AXI exclusive access may look simple at first glance, but as we delve deeper into it, we find the different flavors of exclusive access. The possibility of these different scenarios and combinations poses a tough challenge in verifying the critical feature in AMBA-based designs. This blog primarily focusses on exclusive access in AMBA AXI3, the concept, its different flavors and how Synopsys VIP can be leveraged to overcome the corresponding verification challenges.
During the recent PCI-SIG Developers Conference 2016, held in Santa Clara, CA, there was a lot of interest from attendees regarding Synopsys PCIe Gen4 VIP and source code test suite. One common question that was asked: How do we identify and maintain up to date tests that support the latest PCIe Gen4 specification?
Flash memory first came into home with external storage devices (e.g. USB memory devices) at very modest capacities of few MB and have reached to hundreds of GB. Now it has become ubiquitous with applications across myriad of devices ranging from smart phones, to IoT, wearable and consumer electronics. With the explosion in applications, many flash memory protocols came into existence, and let’s talk about one of them – ONFi.
SAS follows its own version of Moore’s law, doubling the speed every few years. Keeping up with the tradition, SAS 24G (Gen-5) was recently introduced. Let’s decode, how the effective speed has been doubled to 24G, though signaling rate remains at 22.5G. This has been achieved through a more efficient 128b/150b encoding scheme to realize a usable data rate of 24G while retaining compatibility with 6G and 12G. Additional features were also introduced to improve the overall protocol efficiency. Some of the newly added features include binary primitives, primitive parameters, SMP open priority, inter-expander fairness arbitration enhancements, … etc. In this blog we will look into some of the new features, and will continue to delve into more details in the upcoming blogs on SAS.
Synopsys recently announced the availability of industry’s first VIP to support the Serial-attached SCSI (SAS) 24G standard. Let’s look back how far we have come along, let’s time travel and re-live the interesting journey of storage and SCSI evolution.
The PCI-SIG Developers Conference 2016 was held at Santa Clara in last week and it was a great success. Our PCIe experts were there and we bring you the highlights of conference.
Posted in PCIe | Comments Off on PCI SIG Update: Latest on PCIe Gen4 0.7 VIP and Test Suite
Getting the best out of available battery technologies continues to be a challenge for mobile design companies. When phones were used for voice only, the battery lasted a few days compared to less than a day in case of smartphones with high resolution screens, cameras, powerful processors, gigabytes of memories and running power hungry software. Consumers continuously demand more features and functions from their mobile electronics and with more functions converged into a single device, it’s becoming extremely challenging for SoC designs to keep up with the exploding bandwidth, advanced integration functionality and low power constraints.
Verifying today’s complex designs is time consuming, as simulations run for long time and millions of transaction are executed. Traditional approach of debug is to dump all the information of millions of packets in a log file, however it would always be challenging to filter out specific transactions from the huge log file. For example, in case of AXI Protocol, a fixed number of outstanding transactions are allowed during simulation, it would always be difficult to find out such outstanding transaction in the huge log file of a single run of simulation or during interactive simulation. It is one of the biggest pain point of debugging.
The Design Automation Conference (DAC) 2016 was a great success and here we provide you the highlights of Synopsys’ activities at the event.
Posted in AMBA, Audio, Automotive, Camera, CAN, Data Center, DDR, Debug, DesignWare, Display, eMMC, Ethernet, Ethernet AVB, Flash, FlexRay, HBM, HMC, Interconnects, Interface Subsystems, LIN, LPDDR, Memory, Methodology, MIPI, Mobile SoC, ONFi, PCIe, Processor Subsystems, Storage, SystemVerilog, Test Suites, UFS, Uncategorized, USB, UVM | Comments Off on Verification Highlights from DAC 2016
The Design Automation Conference (DAC) 2016, in Austin, Texas kicks off next week starting June 5th to June 9th. As the leading and longest-running annual design and verification event, DAC is the premier place to network with fellow design and verification engineers.
Posted in Audio, Automotive, Camera, Data Center, Debug, DesignWare, Display, Ethernet, Interface Subsystems, Methodology, Mobile SoC, PCIe, Processor Subsystems, Storage, Success Stories, SystemVerilog, Test Suites, Uncategorized, UVM | Comments Off on Synopsys Verification Continuum at DAC 2016