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JESD204B: New Alternative for High-Speed Data Acquisition up to 12.5Gbps

Multiple serial lanes and converters up to 12.5G
Multiple serial lanes and converters up to 12.5G

Can your PCB handle speed up to 12.5Gbps, surprised, right? The JESD204B standard provides bit rates up to 12.5Gbps for serial interfaces. This upgrade allows designers to use fewer transceivers on FPGA/ASIC thereby reducing the I/O count and packaging size. The new standard is being adopted rapidly in high-speed data converter applications such as wireless infrastructure transceivers, software defined radios, medical imaging systems, and radar and secure communications.

Going back 10 years, designers were using the traditional single ended CMOS interface that limited the speed to about 200Mbps. Then came differential LVDS with improved noise coupling on signal lines and power supplies. The limitation of this interface was higher power consumption at lower sampling speeds. This gave the CMOS interface a reason for existence, and it is still being used today. With evolution of faster ADC’s, there was a need of more power-efficient digital interface than parallel LVDS, this urge gave birth to JESD204, high-speed serial link connecting single or multiple data converters to a digital logic device with data rates up to 3.125 Gbps for JESD204A and 12.5Gbps for JESD204B.


In order to select the best converter product that use either LVDS or the various versions of the JESD204 serial interface specification, a comparison of the features and capabilities of each interface is useful. A short tabular comparison is provided in a table below.


Why we care for JESD204B?

  • JESD204B-compliant data converters serialize and transmit data at higher rates thereby reducing number of pins on data converter or FPGA.
  • Simple layout and easier routing, as there are much fewer lanes on board.
  • Smaller package size and reduced cost.
  • Reduced need for skew management, as data clock is embedded in data stream.
  • JESD204B interface is adaptable to different resolutions of data converters. This removes the need for physical redesign of transceiver/receiver (Tx/Rx) boards (logic devices) for future ADCs and digital-to analog converters (DACs).
  • JESD204B standard has simplified multichannel synchronization by using deterministic latency.

It is clear, that JESD204B is the interface of choice for state-of-the-art data acquisition system designs. This standard reduces the number of digital inputs and outputs between high speed data converters and FPGAs and other devices. Fewer interconnects simplify layout and make it possible to achieve a smaller form factor. Stay tuned for our upcoming blogs on JESD204B and JESD204C. To know more about our VIPs please visit

 Authored by Anika Malhotra