Next Generation Memory technologies: Ready to take the verification challenges?
Advancement in Memory technologies and the demand for faster and higher density configuration leaves verification engineers in a limbo. The Memory world is debating the next wave of memory protocols and technologies such as Next Generation DDR, HBM, and NVDIMM:
- DDR: Wishfully the next generation DDR specifications will bring many benefits to computers. With faster and denser memory applications such as Virtual Reality will finally be closer to Reality than ever. Synopsys continues to actively work with the JEDEC standard committees, and the memory vendors, to provide its customers with early access to the next generation DDR VIP that gets as close to the final standard as humanly possible.
- HBM: aka High-Bandwidth Memory is a new type of memory that utilizes vertical stacking technology configuration with low power consumption which is an enabler for ultra-wide communication lanes. The beauty of this technology is the amount of floor plan footprint it occupies. Compared to GDDR5, HBM can fit the same amount of memory in 94% less space! This Memory VIP is currently included in the Synopsys VIP portfolio.
- NVDIMM: aka Non-Volatile Dual In-line Memory Module. This is a RAM DIMM that doesn’t lose its data when power is shut off. This combination of two powerful technologies provides a slew of benefits to improve application performance, data security, and system crash recovery time. Synopsys is working very closely with the memory vendors to capture final details of the technology to be include into the NVDIMM VIP.
Each of these memory types requires its own protocol definition and its own timing and power characteristics. This influx of demands creates a nightmare for the verification engineer whose job is to create a verification environment for the DUT that requires those different memory technologies. Many challenges lurk behind the scenes. Some of those challenges, but not limited to it, are:
- Configuring the Verification model to a specific JEDEC configuration or a specific vendor part when typically, the VIP doesn’t allow configuration updates once the model is loaded into the simulation.
- Developing coverage plans that covers all timings and protocol permutations
- Using a familiar debug environment that’s protocol-aware. Else, different debug techniques must be created and tailored to the memory type used.
Using the Memory VIP from the Synopsys Verification IP portfolio alleviates the aforementioned concerns and challenges. Let me extrapolate:
- For the different JEDEC configuration one don’t need a configuration file for each permutation of the timing possibilities allowed by JEDEC. Using the Memory VIP Virtual Part Selection one specifies the desired configuration parameters and the VIP automatically creates the configuration object based on those parameters. The details of the Virtual part selection will be presented in a subsequent Blog.
- The VIP comes with its own coverage plans that’s specific to the protocol. One starts Verdi with the coverage option turned on, loads the plans, and lets the tool back annotate the results into the plans for analysis.
- Use Verdi as the unified debug platform with Native Protocol-Aware capabilities. And utilize the facility for synchronizing between signals and transactions. This approach hides the low level of details of the front door driven operation.
For more information on these advanced memory technologies, come visit us at our Verification IP demo at MemCon 2016.
Authored by Nasib Naser
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