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DDR-PHY Interoperability Using DFI

The DDR PHY Interface (DFI) is used in several consumer electronics devices including smart phones. DFI is an interface protocol that defines signals, timing, and programmable parameters required to transfer control information and data to and from the DRAM devices, and between MC (Micro Controller) and PHY. DFI is applicable to all DRAM protocols including DDR4, DDR3, DDR2, DDR, LPDDR4, LPDDR3, LPDDR2 and LPDDR.

Why is DFI required?

The DFI interface is not necessary when the MC and PHY are being developed specifically to work together. However, in many situations, the MC and PHY are designed separately – often by different companies. DFI permits companies to develop both MC and PHY IP designs knowing that they will be able to interoperate with the devices developed by other companies.

Additionally, MC devices are primarily clock-based, whereas PHY generally consists of a significant amount of analog logic, therefore the two devices are often developed by different engineers even within the same company. DFI creates a well-defined interface for the two separate design teams.

DFI in Memory System
DFI in Memory System

The latest DFI spec version is 4.0, revision 2. The spec has undergone several major enhancements over the years as shown in following table:

DFI Specifications

Salient Features of DFI Protocol 

  • Different Frequency Ratios – DFI Interface supports 1:1, 1:2 & 1:4 MC to PHY clock frequency ratio for fast PHY memory access. The DFI specification defines a frequency change protocol between the MC and the PHY to allow the devices to change the clock frequency of the memory controller and PHY without completely re-setting the system.
  • No restrictions on MC or PHY – The DFI protocol does not encompass all of the features of the MC or the PHY, nor does the protocol put any restrictions on how the MC or the PHY interface to other aspects of the system.
  • Data Bus Inversion – DBI can be used for reducing the number of transitions on the bus and/or reducing the noise and power consumption on the bus.
  • DFI read and write training operations can increase accuracy of signal placement at higher speeds in DDR4, DDR3, LPDDR4, LPDDR3 and LPDDR2 systems.
  • Low Power Mode – If the PHY has knowledge that the DFI will be idle for a period of time, the PHY may be able to enter a MC-initiated low power state.

Stay tuned for upcoming blogs on DFI and other memory technologies.

Synopsys provides next generation native SV/UVM based VIP for DRAM and Flash memories, and other interface and bus protocols. To know more about our VIPs please visit http://synopsys.com/vip.

Authored by Deepak Gupta.