Flash memory first came into home with external storage devices (e.g. USB memory devices) at very modest capacities of few MB and have reached to hundreds of GB. Now it has become ubiquitous with applications across myriad of devices ranging from smart phones, to IoT, wearable and consumer electronics. With the explosion in applications, many flash memory protocols came into existence, and let’s talk about one of them – ONFi.
ONFi is Open NAND Flash Interface driven by an industry work group of more than 100 companies from the ecosystem of NAND Flash memory. As ONFi protocol evolved, many versions of the ONFi specification were released with increase in speed from ~50MB/s to ~800MB/s. A new mode was also incrementally added to increase the speed in each version of the ONFi as shown in below chart.
ONFi supports the simultaneous read i.e. dual bus support, program and erase operations on multiple die on the same chip. ONFi system is depicted in following diagram.
ONFi supports the multi LUN Transactions that increases the throughput of the ONFi devices. To improve performance to next level by increasing concurrency, ONFi also adds features such as interleaved operations. Interleaving can be used to complete the same operation on different blocks of data concurrently to enhance performance. To reduce the number of CE_n pins and there by the die size, CE reduction mechanism is provided that helps in using single CE_n pin for multiple targets. Typical ONFi device memory structure is demonstrated in the following diagrams.
We will discuss about Toggle NAND, an offshoot of ONFi protocol to customize specific devices, and other flash memory protocols in upcoming blogs, stay tuned.
Authored by Rahul Ramesh Chaudhari.
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