Posted by VIP Experts on July 25, 2016
SAS follows its own version of Moore’s law, doubling the speed every few years. Keeping up with the tradition, SAS 24G (Gen-5) was recently introduced. Let’s decode, how the effective speed has been doubled to 24G, though signaling rate remains at 22.5G. This has been achieved through a more efficient 128b/150b encoding scheme to realize a usable data rate of 24G while retaining compatibility with 6G and 12G. Additional features were also introduced to improve the overall protocol efficiency. Some of the newly added features include binary primitives, primitive parameters, SMP open priority, inter-expander fairness arbitration enhancements, … etc. In this blog we will look into some of the new features, and will continue to delve into more details in the upcoming blogs on SAS.
The support for Gen-5 is not merely a speed bump from earlier Gen-4; but also utilizes a whole new encoding scheme. SAS-4 utilizes 128b/150b encoding scheme that is aimed at providing better link efficiency at speeds 22.5G and higher. To preserve backward compatibility with earlier generations, the 128b/150b encoding is utilized when the physical link operates at Gen-5 or higher (SAS Packet mode). Traditional 8b/10b encoding scheme is used when the physical link operates at Gen-4 or lower speeds (SAS Dword mode).
The 128b/150b encoding process encodes four dwords into 150 bits, whereas the 8b/10b encoding method would have resulted in 160-bits for the same four dwords (lesser number of bits to transmit!). Unlike 8b/10b encoding, the 128b/150b encoding allows for correction of transmission errors at the receiver. In this new encoding scheme, the information is transferred in the form of ‘SPL packets’ which are 150-bit blocks transmitted serially on the wire. Each block contains:
SPL Packet Header
The SPL Packet Header field defines the format of the packet payload descriptor i.e. the type of segment contained in the packet payload.
SPL Packet Payload Descriptor
The Packet Payload descriptor contains a scrambled idle segment, idle dword segment, SPL frame segment or a primitive segment. A simple way to think of packet payload descriptor would be that it is a collection of four dwords of identical type (primitive or data dwords).
Forward Error Correction
The 128b150b encoding scheme also equips the receivers with the ability to correct transmission errors. This is made possible with the Forward Error Correction information embedded in each SPL packet. A Reed Solomon code is used for this purpose. For the computation of FEC, a 26-symbol message M(x) is constructed using the 2-bit Packet header and 128-bit packet payload. Each symbol is 5-bits wide (26 symbols x 5 bits = 130 bits). The parity check symbols P(x) is then calculated over this message M(x). The computed parity P(x) is embedded in the original message and transmitted. The selected Reed Solomon code allows correction of up to 2 symbol errors.
We will look into Binary primitives and Primitive parameters in the upcoming blogs. Stay tuned!
Synopsys recently announced the availability of industry’s first VIP to support SAS 24G.
To know more about Synopsys storage VIP, please visit http://synopsys.com/vip
Also read our recent blogs on storage.
Evolution of Storage Protocols: SCSI to SAS
Industry’s First SAS 24G Verification IP for Enterprise Storage Systems
Authored by Srinivas Vijayaragavan and Pooja Gupta.
A global team of protocol experts that share their insights and technical expertise in the areas of Automotive, DRAM and Flash Memories, Storage, Display, MIPI, AMBA, Ethernet, PCIe, USB and many other bus and interface protocols. This comprehensive team participates in standards committees and will provide the latest information and updates as it relates to your future design considerations.