VIP Central

 

Energy Efficient Designs with MIPI

Getting the best out of available battery technologies continues to be a challenge for mobile design companies. When phones were used for voice only, the battery lasted a few days compared to less than a day in case of smartphones with high resolution screens, cameras, powerful processors, gigabytes of memories and running power hungry software. Consumers continuously demand more features and functions from their mobile electronics and with more functions converged into a single device, it’s becoming extremely challenging for SoC designs to keep up with the exploding bandwidth, advanced integration functionality and low power constraints.

MIPI Alliance has been leading the effort in designing energy efficient interfaces with low and ultra-low power features as cornerstones of its specifications. One of the primary focus in all of the MIPI specifications is to lower power consumption and making the interfaces energy efficient. This blog reviews M-PHY and D-PHY specifications for their energy efficient features.

MIPI M-PHY

MIPI M-PHY [1] is a serial interface technology with high bandwidth capabilities used for mobile applications requiring low pin count and demanding power efficiency. The MIPI  M-PHY Specification features the following aspects for energy efficiency:

  • BURST mode operation for improved power efficiency.
  • Multiple transmission modes with different bit-signaling and clocking schemes intended for different bandwidth ranges to enable better power efficiency over a huge range of data rates.
  • Multiple power saving modes, where power consumption can be traded-off against recovery time. Central to the MIPI M-PHY specification is its Finite State Machine which defines the following five power saving STATEs                                                                                                                                                                                                               
    • STALL: The power saving state in HS-MODE.  This state allows the lowest power consumption of all ACTIVATED states.                                                                                                                                       
    • SLEEP: The power saving state of LS-MODE.  This state allows the lowest power consumption of all ACTIVATED states.                                                                                                                                                  
    • HIBERN8: This state enables ultra-low power consumption, while maintaining the configuration settings.  During this state, the M-RX is considered to be in squelch.                                                        
    • DISABLEDThis is a POWERED state, while MODULE operation is disabled by a RESET signal. When DISABLED, an M-TX shall be high impedance, and an M-RX shall keep the LINE at DIF-Z.                                                                                                                        

MIPI D-PHY

MIPI D-PHY is a flexible, low-cost, High-Speed serial interface solution for communication interconnection between components inside a mobile device. Traditionally, these interfaces are CMOS parallel busses at low bit rates with slow edges for EMI reasons. The MIPI D-PHY solution enables significant extension of the interface bandwidth for more advanced applications. The MIPI D-PHY solution can be realized with very low power consumption.

Operating Modes: Control, High-Speed, and Escape
During normal operation a Data Lane will be either in Control or High-Speed mode. High-Speed Data transmission happens in bursts.

  • Escape Mode: Escape mode is a special mode of operation for Data Lanes using Low-Power states. It shall be supported in the Forward direction and is optional in the reverse direction. 
  • Low-Power Data Transmission: Data transmission happens at low speed (up to 10Mbps) using a low frequency TLPX clock (50ns). In Camera and Display applications, LPDT is utilized during the blanking period to reduce power. Control and status information is send (between camera/display device and the application processor) with the help of low power modules (utilizing low frequency signals).
  • Ultra-Low Power State: When the lane enters the Ultra-Low Power State (ULPS) system goes into sleep state and there is no transmission of data. Almost no power is consumed in this state.
  • Clock Lane Ultra-Low Power State: When the Clock Lane goes into Ultra-Low Power State, the clock transition stops (‘00’ is driven on the lane) and almost no power is consumed.

Low Power Data Transmission
Low Power Data Transmission[2]
Protocols such as Camera Serial Interface, Display Serial Interface, UniPro and Low Latency Interface utilize these and their own features to help create energy efficient designs. We will cover some of these protocols in the upcoming blogs.

Synopsys provides a complete set of MIPI VIP; more details can be found at http://synopsys.com/vip

Authored by Apoorva Mathur.

References:

[1] MIPI Alliance Specification for M-PHY, Version 4.0, 27 April 2015

[2] MIPI Alliance Specification for D-PHY, Version 2.0, 23 November 2015