Posted by VIP Experts on May 10, 2016
We are capturing our memories in high-definition with the latest multi-megapixel cameras and playing back with the high resolution displays. This has led to a tremendous increase in data transfer and bandwidth requirements between peripherals and application processor in a mobile SoC. It’s challenging to support advanced multimedia features in the mobile phones by integrating megapixel cameras and superior resolution displays at a reduced cost and power consumption.
To overcome these limitations, MIPI D-PHY was defined which brought standardization and improved inter-operability and resolved the challenging requirements of higher bandwidth and reduced power and cost. Unlike many of the existing interfaces, MIPI D-PHY is unique because it can switch between high speed and low power mode in real time depending on the need to transfer large amounts of data or to conserve power to prolong the battery life. With the increase in MIPI D-PHY supported data rates up to 4.5Gbps in latest specifications, it is possible to send high bandwidth data over fewer lanes reducing the chip area and number of interface pins. Camera Serial Interface (MIPI CSI-2) and Display Serial Interface (MIPI DSI) are the two packet-based high level protocols that carry image data between the peripheral and the application processor. Both of these protocols use MIPI D-PHY at physical layer.
All lanes travel from the DSI host to the DSI device, except for the first data lane (lane 0), which is capable of a bus turnaround (BTA) operation that allows it to reverse transmission direction. When more than one lane is used, these are used in parallel to transmit data, with each sequential byte in the stream traveling on the next lane. For example, if 4 lanes are being used, 4 bytes are transmitted simultaneously, one on each lane. The display and camera interfaces are lane scalable to save power by switching off the lanes for applications that do not require higher bandwidths.
MIPI D-PHY is gaining popularity with the increasing demand for high end devices that require higher bandwidth. With the increase in bandwidth up to 4.5Gbps, MIPI D-PHY is revolutionizing today’s smartphone market with lower cost and lower power consumption.
To know about Synopsys MIPI D-PHY and other MIPI VIP, please visit: www.synopsys.com/vip
Authored by Ajay Garg
A global team of protocol experts that share their insights and technical expertise in the areas of Automotive, DRAM and Flash Memories, Storage, Display, MIPI, AMBA, Ethernet, PCIe, USB and many other bus and interface protocols. This comprehensive team participates in standards committees and will provide the latest information and updates as it relates to your future design considerations.