Integrate USB Test Suite Quickly to Jump Start Verification
SoC being designed today are getting complex day by day and verification complexity increases exponentially not only due to the complexity of design but also due to the complexity of protocols. Emerging new protocols make it further difficult due to steep learning curve. Writing test cases to cover the entire protocol becomes 3-4 man year job for complex protocols like USB, PCIe, and Ethernet etc. Synopsys provides System Verilog/UVM source code test suites to verify complex protocols. Source code is provided and tests can be extended, and customized easily. You can save the efforts and time by using Synopsys test suites to jump start verification and achieve accelerated coverage closure. In this blog, we will give an overview of the USB test suite focusing on ease of integration and use.
The USB VIP Test Suite provides a common testbench for a type of USB DUT. For example, there is a common testbench tb_dut_usb_device for device DUT and a common testbench tb_dut_usb_host for host DUT. Different testbenches for other possible type of USB DUT are also provided. The testbench for a host DUT connected to a device VIP provides a host driver to translate data objects to DUT specific API sequences. There is also an xHCI driver for generic xHCI register model and memory operations, for example to create a command TRB and write it to a command ring, ring the command doorbell and watch the command completion event TRB. The testbench for a device DUT connected to a host VIP provides a device driver to translate data objects to DUT specific API sequences.
The intended connection with the DUT is achieved using the specific “connection parameter” in the top module. Tests for the intended “connection type” can be run in the testbench. The particular test configures the testbench environment through a configuration object. Testbench level environment (TB_Env) basically consists of two sub-environments: Host_Env and Device_Env, also TB_Env level virtual sequencer and TB_Env level collection of sequences. Host/Device Env consists of Host/Device_Env level virtual sequencer and Host/Device_Env level collection of sequences. So sequence written at the TB_Env level can be targeted to the Host/Device_Env level virtual sequencer. Virtual sequencer at this Host/Device_Env level consists of usb_transfer_sequencer and usb_service_sequencer and virtual_usb_sequencer. In the Host/Device driver, transfer/service received is either processed using the xHCI model (host DUT as USB controller) or can be redirected to virtual_usb_sequencer in Host/Device_Env which connects to sequencers of VIP agent and the processing of transfer/service is done by the VIP.
To integrate Synopsys USB VIP Test Suite to DUT, following SystemVerilog interfaces are used:
- Application Interface – This interface uses the AXI/AHB interface to do CSR (Read/Write) to the controller and DMA accesses to the Memory (_mem).
- Device/Host Interface – This is the USB interface which connects the USB VIP to DUT.
- Device Specific Interface – This interface is used by the driver to poll for interrupts, events and status of the DUT, which will in turn control the USB Test Suite driver.
Figure shown below is an example of testbench for USB controller DUT with following settings:
- DUT Type: USB Device
- DUT Includes PHY: No
- App Interface: AMBA AXI
- USB 2.0 Interface: {UTMI|ULPI} and USB 3.0 Interface: {PIPE3}
In addition to USB test suite, Synopsys provides test suites for a wide range of bus, interface and memory protocols. All the test suites are easy to integrate and easy to use and are provided as source code for extension and customization. For more information on the architecture and scope of the SystemVerilog source-code test suites watch our video blog SystemVerilog Protocol Compliance: Why Source-code Test Suites?
Authored by Karim Aoua
