Synopsys VC VIP provides Verdi Protocol Analyzer, a protocol and memory aware debug environment . In my previous blog Debugging Memory Protocols with the Verdi Protocol Analyzer, I discussed the value add for using the Verdi Protocol Analyzer to debug memory protocols easily and efficiently. Also, I described how easy it is to look at a specific command as a transaction rather than as interpreted signals. In this blog I’m going to show another feature that makes Verdi Protocol Analyzer the tool of choice for debugging memory protocol issues and for validating proper system behavior. Furthermore, the tool can be used for verification of the command sequencer and the interaction between the DUT and the memory models. The feature, we are going to look at today, is synchronizing transactions to the corresponding signals.
To demonstrate the synchronization feature, I chose to use a complex command sequence to initialize the DDR memory. There are 15 DDR memory sequences or steps required for power-up initialization as listed in the Jedec Standard JESD79-4 section 3.3.1. These steps are depicted in the waveform shown in the Figure 3 of standard, as referenced below.
Now let’s take a look at the same power-up initialization steps in Verdi Protocol Analyzer. Here instead of looking at a multitude of wiggling signals one can observe the 15 steps completed as 1 transaction. Furthermore, in Verdi one can highlight the initialization transaction and cross reference the start and end time of the sequence in nWave. This synchronization feature narrows down the area where the user can focus only on the initialization steps without getting bogged down with the other signals and time stamps that are not related to initialization.
This is demonstrated in the following screenshot.
In conclusion, half or more of debug and verification time is cut by the Verdi Protocol Analyzer transaction/signals synchronization feature. Wish you fast and easy debugging.
Authored by Nasib Naser
You can learn more about Synopsys Memory VIP here.