Every hot selling multimedia device today has enviable specifications, but the first thing the user experiences is the display quality. Displays are coming closer to our natural vision by every passing day, thanks to the increasing resolution, and color depths. UHD displays with 4k resolution are being adopted rapidly, and demand for even higher 8k UHD displays is also growing.
Can your PCB handle speed up to 12.5Gbps, surprised, right? The JESD204B standard provides bit rates up to 12.5Gbps for serial interfaces. This upgrade allows designers to use fewer transceivers on FPGA/ASIC thereby reducing the I/O count and packaging size. The new standard is being adopted rapidly in high-speed data converter applications such as wireless infrastructure transceivers, software defined radios, medical imaging systems, and radar and secure communications.
Posted in JESD | Comments Off on JESD204B: New Alternative for High-Speed Data Acquisition up to 12.5Gbps
If you are currently using or consider using JEDEC UFS protocol in your next design you might face several verification challenges. The following blog will talk about 7 of the biggest challenges of UFS stack verification. With the fact that people are moving to reduced pin count and increased speed, an MPHY based stack has picked up momentum and provides an increased number of new applications to leverage the UFS stack. The UFS protocol is being adopted rapidly due to its higher performance, efficiency, concurrent multi-tasking, usage of the complete band width, security, and reliability and longer power life.
Sensors are everywhere surrounding us at home, office, cars, industry and everything else we are using today. It all started with the thermostat and first motion sensor used for an alarm system invented somewhere in 1950s. Over the period of time, rapid increase of sensors used across various applications created significant challenges, there was a need of sophistication in terms of size, electronics, packaging and integration of practically every kind of sensor one can think of. A modern sensor works the same way similar to the sensor decades ago, but is now smaller, better and much more reliable.
In our previous blog on SAS, we discussed about SAS 24G new encoding and features. In the series of SAS blogs, here we shed some light on other generations of SAS that are still hot in the market.
Posted in Data Center, DDR, Debug, DFI, eMMC, events, Flash, HBM, HMC, LPDDR, Memory, ONFi, Storage, UFS | Comments Off on Next Generation Memory technologies: Ready to take the verification challenges?
The two fundamental requirements of every mobile device is speed and power, with the biggest challenge being that both are inversely proportional to each other. One simply cannot have both, because with higher speed comes higher power consumption. With the ever increasing demand for higher resolution graphics and media to enrich the user experience, there has been a significant addition to data processing that requires high speed data transfers. Even though the devices are capable of capturing and playing back high quality media, the storage unit is not fast enough to match the required transfer speeds. This is an out of sync combination and one of the biggest challenges for mobile designs. The problem here is that, a memory system is required to be capable enough to perform read write operations at high speed without adding any significant numbers to power consumption.
MIPI DevCon 2016 was successfully held at Mountain View, California on 14-15th Sep, 2016. Synopsys MIPI protocol experts were there demonstrating our MIPI design and verification solutions for wide spectrum of markets ranging from IoT, to mobile, automotive, and consumer. During the conference Synopsys had several presentations. One of the papers presented by Synopsys was based on a customer case study that provide an overview and successful adoption of the MIPI SoundWire VIP and Test Suites to achieve comprehensive verification and coverage closure on their latest MIPI design.
Posted in Audio, Automotive, C-PHY, Camera, CSI, D-PHY, events, I2S, I3C, Interface Subsystems, MIPI, Mobile SoC, MPHY, SlimBus, Soundwire, Test Suites, UFS, Unipro | Comments Off on MIPI DevCon 2016: SoundWire VIP
The DDR PHY Interface (DFI) is used in several consumer electronics devices including smart phones. DFI is an interface protocol that defines signals, timing, and programmable parameters required to transfer control information and data to and from the DRAM devices, and between MC (Micro Controller) and PHY. DFI is applicable to all DRAM protocols including DDR4, DDR3, DDR2, DDR, LPDDR4, LPDDR3, LPDDR2 and LPDDR.
In today’s connected world of smart devices, we want to access our data faster and at the same time we want it to be secured and protected from intruders. Flash memories are not only faster but secured and reliable also in its avatar as UFS – Universal Flash Storage. This blog provides an insight into various security modes of UFS devices and how to access them. It also points out how encryption is used to secure the data further.