VIP Central

Archive for 2015

 

PCIe Gen4 – VIP/IP Solution with Protocol-Aware Debug and Source Code Test Suites

Today’s PCIe verification engineers have to trade-off between verification completeness and demanding time to market, and the new Gen4 specification makes it more challenging.  This video highlights Synopsys’ complete PCIe Gen4 solution that includes implementation IP (Controller/PHY), Verification IP, protocol-aware debug and source code test suites to accelerate verification closure.

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Posted in Debug, Methodology, PCIe, SystemVerilog, Test Suites, UVM | Comments Off on PCIe Gen4 – VIP/IP Solution with Protocol-Aware Debug and Source Code Test Suites

 

Synopsys NVMe VIP Architecture: The Host Protocol Layers

Our previous post on NVMe was an overview of the NVMe protocol. We will now start looking closer at the VIP-proper, looking initially at the NVMe Host Protocol layers. This will provide an introductory overview of sending commands to the NVMe Controller.

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Posted in Methodology, NVMe, PCIe, UVM | Comments Off on Synopsys NVMe VIP Architecture: The Host Protocol Layers

 

MIPI UniPro: Major Differentiating Features, Benefits and Verification Challenges

MIPI UniPro is a recent addition to mobile chip-to-chip interconnect technology. It’s got many useful features to meet the requirements of mobile applications. That’s perhaps why Google’s Project Ara has selected MIPI UniPro and MIPI M-PHY as its backbone interconnects.

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Posted in Methodology, MIPI, Mobile SoC, MPHY, Unipro | Comments Off on MIPI UniPro: Major Differentiating Features, Benefits and Verification Challenges

 

Get Ready for IoT with Synopsys PCIe VC Verification IP Workshop

Internet of Things (IoT) is connecting billions of intelligent “things” to our fingertips. The ability to sense countless amounts of information that communicates to the cloud is driving innovation into IoT applications. Servers powering the cloud will have to scale to handle these billions of intelligent things. As a preparation to that PCIe Gen 4 has been introduced. It is capable of supporting 16 T transfers/s. Current primary market driver for the PCIe Gen4 application seems to be server storage space.

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Posted in Debug, Methodology, MIPI, MPHY, PCIe, SystemVerilog | Comments Off on Get Ready for IoT with Synopsys PCIe VC Verification IP Workshop

 

Protocol Debug for Complex SoCs

Here, Bernie DeLay, group director for Verification IP R&D at Synopsys, talks to Ed Sperling of Semiconductor Engineering about the challenges of debugging protocols in complex SoCs.

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Posted in AMBA, DDR, Debug, Methodology, PCIe, Processor Subsystems, Storage, USB | Comments Off on Protocol Debug for Complex SoCs

 

MIPI UniPro for PCIe Veterans

The MIPI Unified Protocol (UniPro) specification defines a layered protocol for interconnecting devices and components within mobile device systems. It is applicable to a wide range of component types including application processors, co-processors, and modems. MIPI UniPro powers the JEDEC UFS, MIPI DSI2 and MIPI CSI3 applications. As of now, MIPI UniPro has been adopted the most in the mobile storage segment through JEDEC UFS. Adoption of MIPI UniPro  and MIPI M-PHY provides lower power and higher performance solutions.

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Posted in Data Center, Interface Subsystems, Methodology, MIPI, Mobile SoC, MPHY, PCIe, Unipro | Comments Off on MIPI UniPro for PCIe Veterans

 

The Synopsys NVMe VIP: A High Level View

Overview NVM Express or the Non-Volatile Memory Host Controller Interface (its prior name was NVMHCI, now shortened to NVMe) is a host-based software interface designed to communicate with Solid State storage devices across a PCIe fabric. The current Synopsys NVMe Verification IP (VIP) is a comprehensive testing vehicle which consists of two main subsystems – the first is the SVC (System Verification Component), the second is SVT (System Verification Technology).  The SVC layers are associated with the actual NVMe (and PCIe, etc.) protocol layers.  The SVT provides a verification methodology interface to UVM and other methodologies such as VMM and OVM.

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Posted in MPHY, NVMe, PCIe, Storage, SystemVerilog | Comments Off on The Synopsys NVMe VIP: A High Level View

 

Verifying and Debugging Storage Protocols: SATA

In this video, Synopsys Applications Consultant, Vijay Akkaraju, describes the evolving  Storage ecosystem, the challenges of verifying storage protocol based system, and how Synopsys’ SATA Verification IP can support you in verifying and debugging your designs efficiently and effectively.

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Posted in Debug, SATA, Storage | Comments Off on Verifying and Debugging Storage Protocols: SATA

 

Skip Initialization for DDR VIP Models

In the blog Seamless Fast Initialization for DDR VIP Models, we discussed how important it is for Memory VIP simulations to have the option of going through the process of Reset and Initialization fast, and get to the IDLE state and start reading and writing to memory location. We presented one way to achieve this by scaling down the timings required while going thru all the JEDEC standard steps required for Reset and Initialization.

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Posted in DDR, Memory, Mobile SoC, Processor Subsystems | Comments Off on Skip Initialization for DDR VIP Models

 

MIPI Soundwire Test Suite

Here, we describe how easy it is to integrate and validate a SoundWire design using Synopsys SoundWire VIP Test Suite.

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Posted in Audio, Interface Subsystems, MIPI, Mobile SoC, Soundwire | Comments Off on MIPI Soundwire Test Suite