Today’s PCIe verification engineers have to trade-off between verification completeness and demanding time to market, and the new Gen4 specification makes it more challenging. This video highlights Synopsys’ complete PCIe Gen4 solution that includes implementation IP (Controller/PHY), Verification IP, protocol-aware debug and source code test suites to accelerate verification closure.
Our previous post on NVMe was an overview of the NVMe protocol. We will now start looking closer at the VIP-proper, looking initially at the NVMe Host Protocol layers. This will provide an introductory overview of sending commands to the NVMe Controller.
MIPI UniPro is a recent addition to mobile chip-to-chip interconnect technology. It’s got many useful features to meet the requirements of mobile applications. That’s perhaps why Google’s Project Ara has selected MIPI UniPro and MIPI M-PHY as its backbone interconnects.
Internet of Things (IoT) is connecting billions of intelligent “things” to our fingertips. The ability to sense countless amounts of information that communicates to the cloud is driving innovation into IoT applications. Servers powering the cloud will have to scale to handle these billions of intelligent things. As a preparation to that PCIe Gen 4 has been introduced. It is capable of supporting 16 T transfers/s. Current primary market driver for the PCIe Gen4 application seems to be server storage space.
Here, Bernie DeLay, group director for Verification IP R&D at Synopsys, talks to Ed Sperling of Semiconductor Engineering about the challenges of debugging protocols in complex SoCs.
The MIPI Unified Protocol (UniPro) specification defines a layered protocol for interconnecting devices and components within mobile device systems. It is applicable to a wide range of component types including application processors, co-processors, and modems. MIPI UniPro powers the JEDEC UFS, MIPI DSI2 and MIPI CSI3 applications. As of now, MIPI UniPro has been adopted the most in the mobile storage segment through JEDEC UFS. Adoption of MIPI UniPro and MIPI M-PHY provides lower power and higher performance solutions.
Overview NVM Express or the Non-Volatile Memory Host Controller Interface (its prior name was NVMHCI, now shortened to NVMe) is a host-based software interface designed to communicate with Solid State storage devices across a PCIe fabric. The current Synopsys NVMe Verification IP (VIP) is a comprehensive testing vehicle which consists of two main subsystems – the first is the SVC (System Verification Component), the second is SVT (System Verification Technology). The SVC layers are associated with the actual NVMe (and PCIe, etc.) protocol layers. The SVT provides a verification methodology interface to UVM and other methodologies such as VMM and OVM.
In this video, Synopsys Applications Consultant, Vijay Akkaraju, describes the evolving Storage ecosystem, the challenges of verifying storage protocol based system, and how Synopsys’ SATA Verification IP can support you in verifying and debugging your designs efficiently and effectively.
In the blog Seamless Fast Initialization for DDR VIP Models, we discussed how important it is for Memory VIP simulations to have the option of going through the process of Reset and Initialization fast, and get to the IDLE state and start reading and writing to memory location. We presented one way to achieve this by scaling down the timings required while going thru all the JEDEC standard steps required for Reset and Initialization.
Here, we describe how easy it is to integrate and validate a SoundWire design using Synopsys SoundWire VIP Test Suite.