Verification Central


Celebrating the Holiday Season with VIPs


The Holiday Season is upon us. As you stand in lines, wait for packages to arrive, keep in mind that Synopsys continues to provide you the highest level of service: support, available protocols and deployment of new titles that you, our current and future VIP customer, deserve. It has been a wonderful year — many good memories to cherish, especially with the availability and success of Memory VIP (DRAM and Flash)! We wish you a happy holiday season with family and friends. Thank you for being a VIP this holiday season. Some of the highlights from this year are:

1) At ARM Techcon 2015, we announced the availability of our VC Verification IP for the new ARM AMBA 5 AHB5 interconnect. AHB5 supports the ARMv8-M architecture which drives security into the hardware layer to ensure developers have a fast and efficient way of protecting any embedded or Internet of Things (IoT) device.

2) First Ethernet 400G VIP to enable next generation of networking and communications SoCs, expanding our leadership in 25G/50G Ethernet.

3) Broad library of VIP titles available and successfully in use including USB 3.1, Type-C and Power Delivery, MIPI I3C, and the addition of Ethernet AVB and CAN/CAN-FD to the growing number of Automotive protocols.

4) Test Suite Source Code – that is correct: unencrypted source code is now available for various protocol titles.

5) Webinars and workshops at no charge all year long. We held hands-on VIP workshops on AMBA, Memory and PCIe Gen4 around the world. Stay tuned for more in 2016. If you missed the webinars, you can view several of them now:

We are focused on delivering best in class VIP solutions to you by aligning and collaborating with you on your current and future protocol requirements.

We are glad to have you as a customer and look forward to working with you in 2016. Wishing you have a restful and joyful time.

Cheers and Happy Holidays,
The VIP Experts 🙂

Note: The Synopsys VIP library is a broad library of interface, bus and memory protocols. Based on our next-generation architecture and implemented in native SystemVerilog, Synopsys VIP offers native performance, native debug with Verdi, enhanced VIP ease of use, configurability, coverage and source code test suites. Synopsys test suites are complete, self-contained and design-proven testbenches. Written natively in SystemVerilog UVM, they are provided as source code to reduce or eliminate the challenge of developing a verification environment and tests for protocol-compliance verification. This enables you to easily customize or extend the environments to include unique application-specific tests or corner-case scenarios. These capabilities substantially increase your productivity for one of the most difficult and time-consuming aspects of SoC design and verification.