Verification Central


Debugging Memory Protocols with the Verdi Protocol Analyzer

Debug continues to be one of the biggest hurdles faced by design and verification engineers. While designing a system that requires close interactions with memories, engineers often rely on print statements or waveform viewers to decipher signal behaviors over time, and/or their relationship relative to other signals over time. While this kind of ad-hoc debugging helps in understanding the behavior of a single signal, it does not work well when debugging protocols.

You can learn more about Synopsys Memory VIP here.

This blog post will introduce the Synopsys Debug Platform aka Verdi to debug memory protocols. Several key questions need to be answered during debug, such as:

  • Am I writing to the correct location?
  • Is my physical to logical address translation correct?
  • What type of operation is taking place at a specific memory location?
  • Is my protocol communication between the controller and the memory correct?

Translating waveforms in a complex protocol to commands is a tedious task. For instance, take a look at the DDR4 truth table for the command WRS4 below:


Here, we must interpret each of the address and control signals to realize that the command is indeed WRS4!

Using the Verdi Protocol Analyzer, we can actually see the transaction WRS4, and view it relative to time quickly. As illustrated in the figure below, Verdi Protocol Analyzer encompasses all the necessary analysis tools for a robust, complete, and efficient protocol level debugging:


In subsequent blog posts, I will further discuss how Verdi Protocol Analyzer can be used to debug memory protocols easily and quickly.

Authored by Nasib Naser

You can learn more about Synopsys Memory VIP here.