Verification Central


Synopsys AMBA 5 AHB5 Verification IP: What’s It All About?

This week, at ARM Techcon 2015, Synopsys announced the availability of our VC Verification IP for the new ARM AMBA 5 Advanced High-Performance Bus 5 (AHB5) interconnect. The AHB5 protocol is an update to the widely adopted AMBA 3 AHB3 specification. It extends the TrustZone security foundation from the processor to the entire system for embedded designs. AHB5 supports the newly announced ARMv8-M architecture which drives security into the hardware layer to ensure developers have a fast and efficient way of protecting any embedded or Internet of Things (IoT) device.

AHB5 can enable high-performance multi-master systems with support for exclusive transfers and additional memory attributes for seamless cache integration.  It adds multiple logical interfaces for a single slave interface so you can address multiple peripherals over one bus.

The new AHB5 protocol also enables closer alignment with the AMBA 4 AXI protocol, enabling easier integration of AXI and AHB5 systems. AHB5 also adds support for secure/non-secure signaling so peripherals can keep state correctly. AHB5 also adds support for user signals.


The existing AHB system environment, which is part of the AMBA system environment, supports AMBA AHB2 and AHB3-Lite. Now, we have extended support for AHB5 protocol. Users simply have to change a few configuration attributes and required signal connections for that configuration.

In addition, Synopsys offers advanced system-level capabilities for the ARM AMBA 5 CHI and AMBA 4 ACE protocols. The AMBA 5 CHI is an architecture for system scalability in enterprise SoCs, while AMBA 4 ACE is used for full coherency between processors. The expanded capabilities of Synopsys VIP include system level test-suites, a system monitor, protocol-aware debug and performance analysis. With the growth of cache-coherent designs, checkers and performance analysis are required. The system-level capabilities of Synopsys VIP enable SoC teams to further accelerate time to first test and improve overall verification productivity.

Synopsys VIP features SystemVerilog source code test-suites, which include system-level coverage for accelerated verification closure. The VIP now also offers performance measurement metrics for in-depth analysis of throughput, latency and bottlenecks across cache coherent ports. Synopsys VIP also features system monitors, which interact with other VIP to ensure cache coherency across the system, accurate protocol behavior and data integrity.

To learn more, register for our webinar on November 18th: A Holistic Approach to Verification: Synopsys VIP for ARM AMBA Cache Coherent Interconnects on VIP support for ARM Cache Coherent Interconnects.