Verification Central


ARM TechCon: Optimize SoC Performance with Synopsys Verification IP and Verdi Unified Debug

Companies developing complex ARM-based SoC designs have to constantly keep up with evolving interface standards and proliferating protocols a recurring problem that is resource-intensive and time-consuming. Orchestrating these multiple protocols is critical to extracting maximum SoC performance a key competitive differentiator. Achieving high performance while ensuring correct protocol behavior is best addressed by a combination of transaction-based, protocol-aware verification and debug environments. Synopsys VIP coupled with the Verdi unified debug platform spans verification planning, simulation debug, coverage, HW-SW debug and emulation debug, and helps tackle this challenge end-to-end.


This training session at ARM TechCon 2015 explains how Verdi’s native Protocol Analyzer and Memory Protocol Analyzer help ensure protocol correctness, and how Verdi Performance Analyzer measures individual protocol performance on Synopsys VIP such as AMBA CHI, ACE, AXI. Additionally, the presentation addresses how these advanced capabilities lend themselves to analyzing performance on non-standard SoC interfaces. Capturing dataflow with the Verdi ‘VC apps’ API allows observation of the entire test environment and measures performance at interfaces of interest. Verdi provides a unified environment for designers to analyze this information, uncover actionable insights and drive design decisions to maximize SoC performance.

Please join us at ARM TechCon on Wednesday, November 11.

Speaker: John Elliott  |  Sr. Staff Engineer, Synopsys
Location:  Mission City Ballroom M1
Date:  Wednesday, November 11
Time:  2:30pm – 3:20pm