VIP Central

Archive for November 2015

 

First Ethernet 400G VIP to Enable Next-Gen Networking and Communications SoCs

On Monday, Synopsys announced the availability of the industry’s first verification IP (VIP) and source code test suite to support the proposed IEEE P802.3bs/D1.0 Ethernet 400G standard (400GbE). To understand how it will enable next generation networking and communication systems, we take a look at the evolution of the Ethernet. Evolution of the Ethernet Ethernet was […]

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Posted in Data Center, Ethernet, Methodology, SystemVerilog, Test Suites, UVM | Comments Off on First Ethernet 400G VIP to Enable Next-Gen Networking and Communications SoCs

 

Accelerate your MIPI CSI-2 Verification with a Divide and Conquer Approach

MIPI Alliance’s CSI-2 (Camera Serial Interface) has achieved widespread adoption in the smartphone industry for its ease-of-use and ability to support a broad range of imaging solutions. MIPI CSI-2 v1.3, which was announced in February 2015, also offers users the opportunity to operate CSI-2 on either of two physical layer specifications: MIPI D-PHY, which CSI-2 […]

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Posted in C-PHY, Camera, CSI, D-PHY, MIPI | Comments Off on Accelerate your MIPI CSI-2 Verification with a Divide and Conquer Approach

 

Synopsys AMBA 5 AHB5 Verification IP: What’s It All About?

This week, at ARM Techcon 2015, Synopsys announced the availability of our VC Verification IP for the new ARM AMBA 5 Advanced High-Performance Bus 5 (AHB5) interconnect. The AHB5 protocol is an update to the widely adopted AMBA 3 AHB3 specification. It extends the TrustZone security foundation from the processor to the entire system for embedded […]

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Posted in AMBA, SystemVerilog, Test Suites | Comments Off on Synopsys AMBA 5 AHB5 Verification IP: What’s It All About?

 

ARM TechCon: Optimize SoC Performance with Synopsys Verification IP and Verdi Unified Debug

Companies developing complex ARM-based SoC designs have to constantly keep up with evolving interface standards and proliferating protocols a recurring problem that is resource-intensive and time-consuming. Orchestrating these multiple protocols is critical to extracting maximum SoC performance a key competitive differentiator. Achieving high performance while ensuring correct protocol behavior is best addressed by a combination […]

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Posted in AMBA, CHI, Debug, Methodology | Comments Off on ARM TechCon: Optimize SoC Performance with Synopsys Verification IP and Verdi Unified Debug