VIP Central

Archive for October 2015

 

PCIe Gen4 – VIP/IP Solution with Protocol-Aware Debug and Source Code Test Suites

Today’s PCIe verification engineers have to trade-off between verification completeness and demanding time to market, and the new Gen4 specification makes it more challenging.  This video highlights Synopsys’ complete PCIe Gen4 solution that includes implementation IP (Controller/PHY), Verification IP, protocol-aware debug and source code test suites to accelerate verification closure. Here’s where you can learn […]

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Posted in Debug, Methodology, PCIe, SystemVerilog, Test Suites, UVM | Comments Off on PCIe Gen4 – VIP/IP Solution with Protocol-Aware Debug and Source Code Test Suites

 

Synopsys NVMe VIP Architecture: The Host Protocol Layers

Our previous post on NVMe was an overview of the NVMe protocol. We will now start looking closer at the VIP-proper, looking initially at the NVMe Host Protocol layers. This will provide an introductory overview of sending commands to the NVMe Controller. Here’s where you can learn more about Synopsys’ VC Verification IP for NVMe and for PCIe. […]

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Posted in Methodology, NVMe, PCIe, UVM | Comments Off on Synopsys NVMe VIP Architecture: The Host Protocol Layers

 

MIPI UniPro: Major Differentiating Features, Benefits and Verification Challenges

MIPI UniPro is a recent addition to mobile chip-to-chip interconnect technology. It’s got many useful features to meet the requirements of mobile applications. That’s perhaps why Google’s Project Ara has selected MIPI UniPro and MIPI M-PHY as its backbone interconnects. In this blog post, we describe three differentiating features, benefits and their verification challenges. All […]

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Posted in Methodology, MIPI, Mobile SoC, MPHY, Unipro | Comments Off on MIPI UniPro: Major Differentiating Features, Benefits and Verification Challenges

 

Get Ready for IoT with Synopsys PCIe VC Verification IP Workshop

Internet of Things (IoT) is connecting billions of intelligent “things” to our fingertips. The ability to sense countless amounts of information that communicates to the cloud is driving innovation into IoT applications. Servers powering the cloud will have to scale to handle these billions of intelligent things. As a preparation to that PCIe Gen 4 […]

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Posted in Debug, Methodology, MIPI, MPHY, PCIe, SystemVerilog | Comments Off on Get Ready for IoT with Synopsys PCIe VC Verification IP Workshop